My tristate signals are not being placed in the IOBs. They are clocked signals, always all on or all off, depending on reading or writing, and the registration happens the fabric, not in the IOB. The data_out signals are registered in the IOB's correctly.
I have had this issue before with ISE7.1 and now again with 9.2. In the Synthesis properties under Xilinx Specific Options I changed the defaults Registration Duplication to check and the Pack I/O Registers into IOBs to Yes. No effect.
I really don't want these options anyway. I really only want the tristate signals properly placed in the IOBs along with the data out signals. The defaults should be OK elsewhere.
Can anyone help?
Brad Smallridge AiVision.com