A question for the Xilinx guru's out there:
I am experimenting with the map -bp switch (map slice logic) in order to make better use of device resources.
I am constraining my outputs with IOB = TRUE so that the mapper maps them to IOB flops. When I use the -bp switch, however, I have an output flop that is mapped to a block RAM despite the IOB constraint. The clk-to-out timing specification is unreachable so the map fails with an error message. I have tried applying the IOB constraint in the verilog and in the UCF file.
Is there a way to force the mapper to ignore the -bp switch for certain flops (other than creating and maintaining a mapping file), or am I stuck with having to choose between IOB packed flops and block RAM mapping?
I am using ISE6.1i.
Thanks in advance!
Mark