OrCAD Symbol For Xilinx V2PRO

Hello!

Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I use OrCAD.

Many thanks, Robert

Reply to
Rob
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Hi Rob,

Sorry, but I've never really understood the thinking behind asking this type of question. As a note, it seems like this same question is asked by more OrCAD users than any other schematic capture package.

The reason I don't understand this, is that I don't understand how one can use a generic symbol, or a symbol someone else made for their design, for a part that has 896 pins (or even 300+ pins)? Wouldn't you want to treat parts like this as 1) Heterogeneous...as in, has multiple symbol bodes, and

2) where each body is a function of YOUR design, not someone else's, and not generic (like per bank or something like that)?

Personally, I treat these parts like ASICs, where I use multiple symbol bodies, one for each functional block. That way the design is easily understood, and signals for a specific function can be contained on a single page. For example, PCI interface, 1 symbol. DDR interface, one symbol used multiple times, configuration interface symbol, and a power symbol per bank, and one for VCCAUX & VCCINT (fixed voltages). The later symbols could be "generic" enough, but the former, again, better done for your design IMO.

So, I guess, my suggestion is for you to make your own individual symbol bodies that are specific for the functions of your design. If you're asking for one as a starting point, that makes sense...but...sorry, I can't help you there, I use ViewDraw and Concept ;-)

Regards,

Austin

Reply to
Austin Franklin

Austin:

Yes, I would treat the part as hetrogenous, of course. I would think everyone would have to do that otherwise you would have a part so big that it would be unreasonable to work with.

I would also think that others would build the part by function: power/grnds, diff I/O, I/O, configuration, etc. Actually, much like you have listed below. If you build these types of parts by function it will pretty much suffice for most designs. The large FPGA's that I have built were done in this fashion and I've used them for different projects.

I would think if somebody had this Xilinx part built that it would be segregated in a logical fashion and work fine for me. Furthermore, it would save me MUCH time in building. Obsurd schedules made by unsympathetic management sometimes pushes one to look for ALL the help they can get.

Cheers, Robert

Reply to
Rob

[...]

Howdy Austin,

So when you use that same part for additional designs, you'd rather spend the effort to do a unique 500 or 900 pin symbol for each of those designs rather than making it generic (per bank) to begin with so it only has to be done once? Sounds like a significant amount of extra work.

Regards,

Marc

Reply to
Marc Randolph

Hi Rob,

...well, except for diffI/O and I/O...those are by function, and completely configurable. So, yes, you can "generic-ized" power/gnd and configuration symbols. That leaves a good %70 of the pins non-generic. Using generic symbols for these I/O banks, to me, seems, well, unusable (not my first choice of words) for such a large part due to fact it will poorly document the design, and make for a poor schematic (signals all over the place). A lot changes on these BGAs for PCB routing and internal FPGA timing reasons, as the bondout means you can't necessarily use seemingly adjacent pins.

In the hundred or so FPGAs that I've designed, I've never had one that was exactly the same...I've reused sections, like PCI interfaces, SDRAM, DDR, CameraLink, Configuration...of course. Without knowing what your functions are, it I think it would be hard for someone to offer you any symbols that would work for you.

I guess what I'm trying to say is you may not find what you are looking for, and if you do, it may not be what you really want. Just MNASHO. It takes me a number of hours to make a new FPGA or ASIC symbol, and I get exactly what it is I want.

I thought OrCAD was purported to be easier than most other schematic capture programs to create symbols in? I used it a number of years ago, and found I didn't like it...but was told I just wasn't good with it, which was true enough...but OrCAD still seemed obtuse to me.

Regards,

Austin

Reply to
Austin Franklin

Rob,et.al.

Oleda technologies has a web-based tool that will create heterogeneous Orcad or Viewlogic schematic symbols for your parts. Fully functional trial-accounts are available. Your symbols can be generic which use the Xilinx pin descriptions for pin lables, or they can be based off of the UCF, or PAD file for your design which allows the use of your design signal names for the pin labels. The symbol set can be partitioned based on the architecture, a symbol for each IO bank, one for power and ground, configuration etc, or it can be partitioned by function based on your signal names. You can also generate symbols for footprint compatible parts which will check your pin assignments against all the parts which are available in the same family and package. Pins with NCs in one or more parts will be annotated on the symbol. This tool provides a very quick way to generate custom schematic symbols for any design. A graphical editor is available to examine or reposition pins after you have configured your symbol set. You can move pins between symbols or reposition pins on a symbol etc. In addition to generating the symbol, it generates a cross-reference table which can be helpful in documenting your fpga or checking your schematics.

Oleda also has a program called PCB_Review which will examine the FPGA connections in your PCB netlist file and compare them to your FPGA design. It will check all the power and ground pins and the decoupling caps. It checks VREFs for IO standards which require them. It checks the configuration pins, looks for pullups on done, Init etc, checks DCI resistor connections, trace out your JTAG chain for multiple FPGAs etc. It will look at your the signal connections for the design and report any FPGA signals which are not connected to nets on the board, or any board nets which go to pins without an FPGA signal assignment in your design. Differential signal pairs are checked to match pairs on the board to pairs on your design and against the IO standards in your UCF. It will check and report termination resistors on each signal in your design. A table of all the connections for your FPGA is generated. This is definitely a set of tools that will help with "Obsurd schedules made by unsympathetic management".

John

Reply to
pipjockey

Duh, I forgot the link! Oleda Technologies can be found at

formatting link

John

Reply to
pipjockey

Hi Marc,

Correct. I do reuse symbols I've already made, obviously, and it may require a pinning change. For new symbols, I take an existing one, and re-do it.

No, not really. It is far less work, and makes for far more usable (clean and able to be followed and better document the design) schematics since I don't have to hunt around for pins, draw busses to many different places, cross pages for logically grouped functions etc. I've done both, and my current method works far better for my needs.

It really is a matter of whether you simply consider your schematics simply a netlist or a document. I consider my schematics documentation, and need them to be as descriptive as possible of the design, as well as easy to logically follow so others can garner the gist of the design easily.

Regards,

Austin

Reply to
Austin Franklin

The reason that ORCAD users seem to ask this question more often than most is because this bit of the tool is poorly documented. You can easily copy/paste from EXCEL.

1) Get the pinout into two columns in excel, pin number and description. You can play with the fitter ouput to get this for your design or use the excel files that Xilinx provide. However the generic xilinx tries to document every IO possibility on each pin. 2) Select the pins in a column and ctl C 3) Place a pin array onto a symbol with the number of pins that you need, of type IO. 4) Select the pins and ctrl E. 5) Select the column you want to paste into and shift insert.

Change the pins that aren't IO into whatever.

Colin

Reply to
colin_toogood

Oleda Tech has the answer. Anyone out there looking to create a part should stop by this site. You can create a part by bank or user-defined function. This package is sweet. I put together the Xilinx part in minutes. I saved myself hours of work.

This is a MUST see package.

Reply to
Rob

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