I am trying to get rams in xilinx to synthesize in synplify pro. I am a novice in syplify pro. I used the core generator to generate BRAM and then since for brams we cannot generate edif files I used ngc2edif to convert it to .ndf. I then added these ndf files into the project. Howewver I seem to get an error with the synplify pro.The core is a simple dual port RAM with a write port A and a read port B The error is following. I dont know how the synplify pro picksup the component from unisim. I have given the components name as ramb16_s18_s18.
ERROR : Port web of entity unisim.ramb16_s18_s18 is unconnected
The error is regarind port web which is a writ eenable prot of b . but port b is just a read port with we disabled.