I used the syn_preserve synplify attribute in my VHDL code as below.
attribute syn_preserve of sign1: signal is true;
Modelsim gives compilation error for this? Any help to rid of this would be appreciated.
Thanks, Muthu
You are probably missing the declaration of the attribute.
attribute syn_preserve : boolean;
snipped-for-privacy@rediffmail.com wrote:
Alternately, you could include the Synplicity library, which defines the attributes. But I typically do it the way Ken suggested.
JTW
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