Hi all,
I am looking for a generic set of TCL commands (for Synplify) to constrain _all_ flip-flops which are connected to the same clock enable net with the same timing constraints. This would be much easier than constraining every single net on its own. I suppose there should be a set of TCL commands to d efine those timing constraints. Let me give you an example: I have a CLK frequency of 40 MHz (rising edge) and all flip-flops in this example design are connected to a clock enable s ignal. This enable signal takes care that only every second rising edge clo ck signal is considered. Therefore I want to define a multi-cycle path cons traint of "2" for all those flip-flops connected to this clock enable signa l.
Does anybody have suggestions for such a set of TCL-based timing constraint s?
Thanks in advance.