Hello!
If I use the CoreGenerator (for example in order to configure a Dual Port Ram) do I have to copy the source code generated by the CoreGenerator in a vhd-file or is it enough to add the generated core (-> including the xco-file by saying: "New Source... IP(CoreGen & Architecture Wizard) in Xilinx ISE Foundation)? Isn't it possible just to use the xco-file, generated by the CoreGenerator? Or do I have to add a vhd- file in addition?
Tobias.