Addressing BRAM in a V2 pro

Look at Xilinx's website for an appnote. It is not difficult to interface with BRAM's.

It is simple and straightforward, but remember that reading (as well as writing) requires a clock. And you must provide stable addresses a set-up time before the active clock edge, not only for writing, but also for reading. Peter Alfke, Xilinx, from home.

Short coding example (from the real life):

--snip type memory_type is array (natural range ) of std_logic_vector(0 to 31); signal memory : memory_type(511 downto 0);

--snap

--snip bram_inst : process(clk) is begin if rising_edge(clk) then if rst = '1' then data_out '0'); else if fifo_write = '1' then memory(to_integer(write_addr))

Hi

tanks for the help

I have looked up the appnote for using BRAM and the PLB-bus. They speak of "IP2IP_Addr but what those that means? I think I don't have addresses in my IP or do I have them and I don't know about it. How can you have addresses in your IP?

Can anyone tell me more about this?

Greets Mich

you need to read the IPIF documentation, this is an middle IP layer that is used to connect things to OPB and PLB

antti

But I have attached my IP and the BRAM on the PLB why the connection between OPB and PLB

Mich