# Can I use Verilog or SystemVerilog to write a state machine with clock gating function? - Page 3

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Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Sigh, can't believe I keep letting myself get dragged into these
discussions...

Weng - what you're completely missing what many have been telling you -
your definition of a "state machine" is so broad that it's essentially
meaningless.  Since you think that YOUR definition of a "state machine"
includes this 6M L2 cache, then as Ken and I have tried to tell you,
your "state machine" definition includes the subset of ALL synchronous
machines.

This isn't a terrible definition of a state machine, (but one that
doesn't offer much utility). But this just goes to show you that any
Super Snazzy Ideas you've got have already been shown in prior art, in
the general set of all synchronous machines, as Ken's trying to
communicate to you.

I fear you'll ignore this information as you've ignored most of what
information others have tried to communicate to your in the past (in
this thread and others).  But I'm saying it anyway.

I'll await your reply with more sets of patent result hits from

Regards,

Mark

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Regards,

Mark

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Mark,

Here is the definition of a state machine introduced in my prior art part:

[0003]    Traditionally a deterministic finite state machine is mathematica
lly defined as a set of 6-tuple M = (?, ?, Q, q0, ?, ?
?), where ? is a finite set of input symbols, ? /= 0 is a fin
ite set of output symbols, Q /= 0 is a finite set of states, q0 ? Q
is the ?reset? state, ?(q, a) : Q x ? ? Q
is the transfer function, and ?(q, a) : Q x ? ? ? i
s the output function.
[0004]    Conventional state machine theory has following State Machine Axi
om:
[0005]        State Machine Axiom        A state machine has one and only one state
being active on any cycle after the state machine is properly initialized.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

This definition matches all synchronous digital circuits.

Regards,

Mark

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Mark,

"This definition matches all synchronous digital circuits."

Do you plan to retrieve the following claiming?

"Weng - what you're completely missing what many have been telling you -
your definition of a "state machine" is so broad that it's essentially
meaningless."

I really don't understand what you are saying.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Do you mean will I retract my statement?  No I won't because it's
consistent.  The definition you listed in the grandparent post of a "state
machine" has such a broad scope that EVERY synchronous digital circuit
in existance fits the definition.

You can prove me wrong by counter-example.  I assert that your
definition of "state machine" is so broad that any synchronous digital
circuit will match your definition.  If you can show/explain ANY
synchronous digital circuit that does NOT match your definition of a
"state machine" you'll have falsified my assertion.

I can come at it from the opposite end and suggest a few example of
synchronous digital circuits that one normally wouldn't think of as
"state machines" but fit your definition none-the-less.

But I think the excercise (of trying to come up with a counter-example)
would help you understand what we've been trying to communicate to you.

Regards,

Mark

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Am Mittwoch, 9. Januar 2019 23:07:47 UTC+1 schrieb gtwrek:

ically defined as a set of 6-tuple M = (?, ?, Q, q0, ?,
?), where ? is a finite

/= 0 is a finite set of states, q0 ? Q is the ?reset?
? state, ?(q, a) : Q x ? ? Q

is the output function.

Axiom:

te being active on any cycle after the state machine is properly initialize
d.

Yes, that's true. A FSM could be a dedicated statemachine written in one HD
L module, but each counter is a simple FSM and each complete logic design c
an be seen as a statemachine.

Every part of a statemachine containing at least 2 states and 1 input and o
utput is itself a statemachine and every combination of 2 statemachines is
one statemachine. FSM is just a model to describe a digital circuit with at
least one sequential element.

best regards Thomas

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/10/19 5:25 AM, Thomas Stanka wrote:

Perhaps some would call ANY synchronous digital circuit a state-machine,
but the more classical definition would imply that it be a system with a
single clock domain as it is the transformation from one 'State' to
another 'State' on *The* clock edge, with the definition of the Next
State being a function of the Previous State and the Inputs. The concept
of previous and next imply a singular concept of time steps, thus a
single clock domain (though clock gating/enables of that domain would be
allowed).

A system using multiple, not tightly related clocks, would fail that
definition, and in the FSM view of the world would be multiple
intertwined State Machines. Most digital system can be viewed as a set
of coupled FSMs based on the number of clock domains in the system.
Poly-Phase systems and system using wave phasing (multiple clocks
between registers) stretch the concept of a State Machine a bit, but can
probably be reasonably described as such. Some systems with Asynchronous
bits can get harder to describe as a FSM.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Yes, exactly.  The qualification of a single clock - or as you note -
related clocks is what I was trying to cover with the term SYNCHNRONOUS
digitial circuits.   In one of my post up the thread I mentioned a
single clock - Kevin more correctly labeled the requirements as
SYNCHRONOUS which I think summarizes the requirements better so I took
that label.

I'll say again, any SYNCHRONOUS digital circuit meets Weng's definition
of a state machine.

Regards,

Mark

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/10/19 10:37 AM, gtwrek wrote:

My terminology divided Synchronous (transitions happening on the edge of
some 'global' clock) vs Asynchronous, where some device changes its
state independant of the main clocks, perhaps with an asynchronous
set/clear or being clocks by some input signal that isn't considered a
system clock.

Synchronous system can be divided into single domain and multi-clock
domain systems, for which you seem to want to define 'Synchronous' as
what I would consider 'Single Clock-Domain Synchronous'. Multi-clock
domain synchronous system tend to not be define as *A* FSM, but can be
as a set of FSMs that interact.

Proper multi-clock domain systems need a bit of care at the domain
boarders to avoid meta-stability issues, but this isn't really that hard
to handle.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 11/01/2019 15:12, Richard Damon wrote:

.. snip
what?

the opposite, it is really hard to handle unless you have a single
signal moving from a slow to fast clock domain. Why do you think there
are so many (quite expensive) CDC tools (Bluepearl, Spyglass, Questa
CDC, Conformal, Meridian, ..)  Have a look at past ASIC user surveys
(like Wilson research group) and you will find that CDC errors are the
number 2(!) reason for a respin, I would say that qualifies as a hard to
handle issue given the cost of a respin nowadays.

Trying to a find a deep convergence,  reset or a CDC glitch problem in a
30 clock domain design (not that unique) is not for the faint-hearted
and that is after identifying that it/they exists in the first place
(simulation won't show you unless you use CDC-FF models from your CDC tool).

Time to power cycle my TV box again as it got stuck yet again....;-)

Hans
www.ht-lab.com

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Friday, January 11, 2019 at 3:04:01 PM UTC-5, HT-Lab wrote:

n
f
d

l).

A customer asked me how I handle multiple clock domains and I told him that
unless there was reason to perform significant processing in multiple cloc
k domains I transition all I/Os to a single clock domain as quickly as poss
ible so that all interaction between circuits are then in that one clock do
main.  The resulting domain transitions are limited and well defined making
them easy to debug.

Rick C.

--+ Get 6 months of free supercharging
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Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/11/19 3:03 PM, HT-Lab wrote:

Solving clock domains issues is fairly straight forward when they are
identified at design time. You do need different strategies depending on
the basic case you are working in, is it a single signal, or is it a
bus, are we going fast to slow and need to make sure the signal gets
across, etc. What is hard is to verify that you have detected all the
cross domain transitions and performed the needed mitigations for it.
They can also get harder if you are trying to squeeze every last drop of
performance out of a cross domain connection.

I suppose some things get mentally hard to shake, like making the
assumption that your synchronous clear terminates simultaneously in all
domains (instead of the idea that simultaneity isn't really a concept in
a multi-clock domain system.)

The other issue is that when you start to move to higher level
abstractions the real RTL code, it becomes easier to miss the cross
clock domain transfers or to miss some of the interactions between
multiple instances of a given cross-domain transfer (Two signals that
are together in clock domain 1 will not necessarily be together in clock
domain 2 after transitioning, unless care is taken to keep them together).

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

To be clear here - my definition of a "state machine" matches what I'm
sure most of the other poster's here define it as.  A small (less than
5-6 bits) number of states, operating on a single clock domain.  Small
enough such that a Synthesis Tools can apply a model to, where as the
"state labels" can be disassociated from the actual bit encodings (and
number of bits).  Such a tool can then re-encode these bit encondings
(and number of bits) in order to optimize the circuit, balancing such
metrics as power, timing, area, soft-fault tolerance, and errant state
detection.  Such a re-encoding would preserve all state transitions, and
output products - but change the underlying bit-encodings.

Anything more than 5-6 bits (I don't think I've ever designed any with
more than 4) would call (in my opinion) for some re-partitioning and
redesign.  In fact, I'd wouldn't be surprised that even with todays
modern tools, a FSM optimizer would start choking when you reach 8-10
bits.

Now, again this is all just a MODEL that we can apply as people to
a digital, synchronous, single-clock domain circuit.

Weng seems to be applying a looser definition of "state machine" that
he's applying to model a CPU Cache circuit (with a ginormous number of
states, or perhaps a ginoromous number of small, indepenent state
machines all interacting).  That's fine to model it as such, if there's
some sort of benefit to having this model.    (I think it's a silly
model to make, without any benefit, but *shrug*)

My only argument, which I still don't think he understands, is with his
loose of a definition, one can apply his "state machine" model to
ANY digital single-clock domain synchronous circuit.  (I just wanted to
avoid that last mouthful and just say "synchronous".)

Weng further goes on and says, with this "state machine" model of a CPU
cache, he can now apply some secret algorithm to optimize something.
My (and other's) points here were that if his algorthim when applied
under his "state machine" model for a CPU cache, would also apply to ANY
other digital single-clock domain synchronous circuit.

Many then would point out, that this would then all fit well within
established prior art.  Transformations of Clock Enable circuits to
Gated Clocks are well understood to both the tools and designers.
As per normal, the devil is all in the details of the cost/benefit
metrics of making such transformations.

(And also pointing out, I'm completely unclear as to what Weng's super
snazzy algorithm is, under what conditions it could work, what it's cost
could be, etc.)  Some of his post seems to talk about low power and magic
clock gating, but none of it is very clear.)

Regards,

Mark

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Friday, January 11, 2019 at 5:03:35 PM UTC-5, gtwrek wrote:

This seems to be par for the course with patent seeking.  The typical paten
t seeker is not proficient or even familiar with a given area of expertise,
has ill-conceived ideas of what the tools can do or how the tools work and
proposes poor solutions to issues no one else sees as problems.

I would be interested in learning of such a patent seeker's background and
what sorts of work they have done in the past.

Rick C.

-+- Get 6 months of free supercharging
-+- Tesla referral code - https://ts.la/richard11209

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi Mark,

Is there anywhere I said that
"Weng seems to be applying a looser definition of "state machine" that
he's applying to model a CPU Cache circuit (with a ginormous number of
states, or perhaps a ginoromous number of small, indepenent state
machines all interacting)."

I only said that one L2 cache line has a state machine, and 6M L2 cache would need 100,000 state machines.

And snipped-for-privacy@gmail.com resolved my problem accurately and excellently.

Invincible! Marvelous! Smartest!

Thank you, snipped-for-privacy@gmail.com.

Weng

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On 1/11/19 5:03 PM, gtwrek wrote:

The basic concept of a state machine is that given a state variable S
(implemented with some number of bits and representing states like S0,
S1, S2, ... Sn), and a set of inputs I, then we can say that we have the
logic that at the clock signal

S <= F(S, I)

where F is a pure combinatorial function if its inputs.

Technically, most single clock domain sychronous systems qualify by this
definition, but I agree that 'arithmetic' and other data-path type
structures are really state machines.

I have designed state machines with perhaps as high as 100 state
(slightly above your limit), and machines of that size that I have done
tend to have a number of legs where once you get to state Sn, you
automatically progress to state Sn+1, Sn+2 ... Sm and you could perhaps
factor out a smaller state machine coupled to a counter.

Based on the papers Weng pointed to, he is dealing with this sort of
state machine, as they are presents as perhaps a dozen circles with
conditions and outputs on the arrows between them, and a very large
number of these in the system.

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Am Mittwoch, 9. Januar 2019 06:31:03 UTC+1 schrieb Weng Tianxiang:

clock input.  'Clock enable' signals do not modify the clock in any way."

FF will keep unchanged on the next cycle. If a CLOCK ENABLE is asserted, a
clock pulse will feed a FF, and the FF will be updated on the next cycle.

In theory a "clock enable" gates the clock line, but in reality it usually
switches only the data path to the FF.
In most technologies the enable of a FF with Clock enable is synchronous us
ed.
If you zoom into a typical clock enable-FF you will find the following hard
ware implemented.
(use fixed font for view)

_________________________
|                        |
|  +---+   +-------+     |
--|   |   |       |     |
|MUX|---|D     Q|-----------
D ----|   |   |       |
+---+   |   FF  |
|     |       |
Enable-------     |       |
|       |
Clock ___________|\      |
|/      |
+-------+

A clock tree is the tree of buffer (inverter) between clock source and each
FF and the gating is often performed on a dedicated branch of the clock tr
ee which is no leaf.
It is ofc possible and most flexible to gate the clock direct before the FF
(and therefore at the end of the leaf) but this has the least power saving
effect and the worst impact in resource usage.
The best effect is gained when gating as near as possible on to the clock s
ource.
On the other hand this is not trivial as the clock tree without any clock g
ate would connect maybe 8 FF that are functional close together on same lea
f of the clock tree but if of these 8 FF only one should be gated than you
need to move the gating FF from non gated branch to a gated branch which mi
ght connect this FF to some other FF that are pyhsically located further aw
ay increasing routing effort and routing delay.

In many cases the power consumption of the clock tree switching with clock
gating only on the FF itself is not smaller than the power consumption of t
he same tree with synchronous data gating as the FF itself is in both imple
mentations keeping its outputs constant when "gated" and the load of the FF
located clock gate is same as the load of the FF.

The synchronous enable has from timing point of view a strong advantage vs
clock gating and is therefore easier to handle in layout.

regards,

Thomas

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Tuesday, January 8, 2019 at 6:23:40 PM UTC-5, Weng Tianxiang wrote:

ing function, no matter whether or not it is coded to have clock gating dev
ice!

Then your invention will optimally use the toggle flip flop as the fundamen
tal storage device.  There are several flavors of basic flip flops:  SR (se
t-reset), JK (improved set-reset), T (toggle) and D.  The industry has long
since settled on using essentially only the D type and presumably has opti
mized that one.  So to use your invention one would have to either use a no
n-optimal flip flop or construct it from the D type, which presumably would
be less optimal than if it were a true T type.

If the industry had settled on using only T flip flops then we would all be
doing gated clock designs now.  But just because it hasn't does not mean t
hat the T flip flop and the associated gated clock logic required to use th
at flip flop type is not already existing prior art.  It is simply prior ar
t that is not widely used.  A single logic description can be synthesized t
o use any of the basic flip flop types inherent in the underlying hardware.
So the mapping of some VHDL/Verilog source code to be implemented using T
flip flops as storage is not novel.

While nearly every invention is a new novel use that builds on prior art yo
ur apparent claim here "all state machines will be synthesized to have cloc
k gating function" is nothing more than stating that "all state machines wi
ll be synthesized using T flip flops" which is neither new nor novel.  The
limitation to "all state machines" rather than "all memory storage" is a re
striction over what is already existing so that is not novel either.

Kevin Jennings

Re: Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
On Tuesday, January 8, 2019 at 4:47:13 PM UTC-5, Weng Tianxiang wrote:

how do you handle it using your scheme?

t

a chip" at this FPGA group several years ago.

list only the search word "L2 cache inassignee:intel" and you can find thro
ugh Google there are 4,830 patents filed and issued by Intel, the search wo
rd "L2 cache state machine inassignee:intel" and it leads to 4,360, each of
them is related to a type of state machines.

it designer if he does not seriously consider or design a state machine.

and Altera. Reading Xilinx and Altera' patents gives me the knowledge on ho
w they design their FPGA chips. Reading Intel, IBM and AMD' patents gives m
e the knowledge on how they design something very complex and new technolog
y trend. And through the reading I find many topics for me to further devel
op.

into low power mode in response to special bus cycles executed on the bus"

ne
wer power status, no matter what type of state machines is, and the logic r
esource usage is less than a conventional synthesizer would generate.

I would estimate it is approximately the same amount of logic in general.
"

n "WState /= WState_NS". Is it obvious to you?

If you can perform an equality comparison without using gates, that will be
of tremendous value in logic design.  Instead of using conventional gates
all logic can be decomposed to an expression using equality comparisons (th
e equivalent of the XOR applied to bits followed by an OR gate).  So if you
can perform the not equal comparison on a multi-bit word without gates, th
en every digital logic design can be implemented with no logic gates at all
!

By all means patent that and the world will beat a path to your door!!!

But obviously what you said is not true.  So I must be misunderstanding you
.

Perhaps you can explain what you really mean.

Rick C.

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