Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx timing parameter definitions? e.g. Tbxcy, Tcinck, etc? Where are they defined?
Hi FPGA Folk, Is there any xilinx or other documentation that describes what these symbols mean? E.g. Tcko, Tbxcy, Tcinck? The FPGA datasheets define a small subset of all the possible parameters...
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15 years ago
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xilinx v5 ddr2 controller
Hi, I have used the core generator for a DDR2 controller and I'm trying to implement my own user application. In my current simulation the controller comes out of calibration but when I try to write...
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15 years ago
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pci bridge fpga card
I have an AMIRIX board ap1070 . There is a pci bridge (POWERSPAN II ) from TUNDRA on the board which provides the interface communication between the fpga and the pci card. The AMIRIX has given me the...
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15 years ago
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First CPLD project
Hi All, I'm doing an internal project for my tiny company and have chosen to use a Xilinx XC9572 and an Atmel ATMEGA324P along with 6 74LS245 transceivers for this portion. This project is a board to...
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15 years ago
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xilinx core generator
Hello, Im new to Xilinx core generator tool and have a very fundamental question. I want to generate a single port RAM with an enable signal for the READ operation and the WRITE operation. The write...
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15 years ago
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GTP simulation problems
Hi, since I updated to ISE 10.2 and regenerated my GTPs with coregen I have simulation problems. All output values from the GTP models are X although ALL input values driven by the toplevel module are...
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15 years ago
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Reading FPGA internal memory data
I have some IP output data written in an Altera FPGA memory inside the FPGA. I have two questions here 1) How can I read the FPGA memory I use USB blaster cable for this? 2) Can I somehow dump the...
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15 years ago
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usb core
is any bug in usb core 2.0 in open cores site.
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15 years ago
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How to prevent mapper stripping when synthesizing without IO buffers?
Hi, I have designed a VHDL entity that is a subset of the complete design. I have verified its functionality with a simulation in modelsim and now I want to run it through the xilinx synthesis(XST)...
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15 years ago
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Mismatch simulation & post sythese results
Hi I am a little bit desperate at the moment. My design is working fine when simulating in with Modelsim. Also the sythesis process works fine but when I check the register content at the end of the...
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15 years ago
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mean of ddfs
its is direct digital frequency synthesiser
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15 years ago
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Using VHDL packages
Hey there, I have asked this question in another forum as well but that forum ha gone into the 2nd page and I am not sure how many people would bother goin to the next page. Anyways, I am trying to...
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15 years ago
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Why cant XST sythesis this piece of code
Hi When running XST then XST is analysing an entity for ages that contains the following piece of code. if (signal1 = '1') for I in 0 to 15 loop if (signal2(I) = '0') then...
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15 years ago
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Strange ddr controller bugs.
Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller tester to test the DDR interface of FPGA(virtex5), after a long time run it appers...
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15 years ago
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The Code One
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15 years ago
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