Hi,
since I updated to ISE 10.2 and regenerated my GTPs with coregen I have simulation problems. All output values from the GTP models are X although ALL input values driven by the toplevel module are defined (0 or 1).
Actually some input values are X but these are derived from a DCM which is again driven by the PLL lock detect (from the GTPs) so the main problem is that the PLL does not lock I guess. (however its X and not zero) The CLKIN and all resets are definitely fine.
Any ideas?
On 7$B7n(B14$BF|(B, $B2 Hi,
I don't think it necessary to regenerate the IP core if you already have the previous version of the IP core. Maybe you just keep the *.ngc file maybe the GTP block has not compiled or recongonized by modelsim. will cause the error.
Hi,
I need a GTP design which I can modify and regenerate.
I am using cadence ncsim.
regs, He> On 7$B7n(B14$BF|(B, $B2
you should check your reset signal. when you simulate it, it must remain asserted for atleast two clock cycles and then deassert. in your simulation code, for exp. if your clock cycle is 100ns
#0 rst=1'b1;// (for active high reset)
#200 rst=1'b0;
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