Latest threads in Field-Programmable Gate Arrays

Xilinx timing parameter definitions? e.g. Tbxcy, Tcinck, etc? Where are they defined?

Hi FPGA Folk, Is there any xilinx or other documentation that describes what these symbols mean? E.g. Tcko, Tbxcy, Tcin...

1 18yrs

andrew.newsgroup

1 18yrs andrew.newsgroup

xilinx v5 ddr2 controller

Hi, I have used the core generator for a DDR2 controller and I'm trying to implement my own user application. In my cur...

2 18yrs

kal

2 18yrs kal

pci bridge fpga card

I have an AMIRIX board ap1070 . There is a pci bridge (POWERSPAN II ) from TUNDRA on the board which provides the inter...

0 18yrs

nbg2006

0 18yrs nbg2006

First CPLD project

Hi All, I'm doing an internal project for my tiny company and have chosen to use a Xilinx XC9572 and an Atmel ATMEGA324...

3 18yrs

gregbdelete

3 18yrs gregbdelete

xilinx core generator

Hello, Im new to Xilinx core generator tool and have a very fundamental question. I want to generate a single port RAM...

3 18yrs

nairvan

3 18yrs nairvan

GTP simulation problems

Hi, since I updated to ISE 10.2 and regenerated my GTPs with coregen I have simulation problems. All output values from...

3 18yrs

heinerlitz

3 18yrs heinerlitz

Reading FPGA internal memory data

I have some IP output data written in an Altera FPGA memory inside the FPGA. I have two questions here 1) How can I rea...

2 18yrs

bajajk

2 18yrs bajajk

usb core

is any bug in usb core 2.0 in open cores site.

1 18yrs

hmmudassir82

1 18yrs hmmudassir82

How to prevent mapper stripping when synthesizing without IO buffers?

Hi, I have designed a VHDL entity that is a subset of the complete design. I have verified its functionality with a sim...

4 18yrs

andrew.newsgroup

4 18yrs andrew.newsgroup

Mismatch simulation & post sythese results

Hi I am a little bit desperate at the moment. My design is working fine when simulating in with Modelsim. Also the syth...

5 18yrs

RobJ

5 18yrs RobJ

mean of ddfs

its is direct digital frequency synthesiser

0 18yrs

roji.sweet

0 18yrs roji.sweet

Using VHDL packages

Hey there, I have asked this question in another forum as well but that forum ha gone into the 2nd page and I am not su...

1 18yrs

kamran.wadood

1 18yrs kamran.wadood

Why cant XST sythesis this piece of code

Hi When running XST then XST is analysing an entity for ages that contains the following piece of code. if (signal1 = '...

2 18yrs

Clemens

2 18yrs Clemens

Strange ddr controller bugs.

Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller test...

6 18yrs

dadabuley

6 18yrs dadabuley

The Code One

http://www.thecodeone.com/vb/index.htm

0 18yrs

hesham.hamdy

0 18yrs hesham.hamdy

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