Field-Programmable Gate Arrays

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pci bridge fpga card

I have an AMIRIX board ap1070 . There is a pci bridge (POWERSPAN II ) from TUNDRA on the board which provides the inter...
0 comments posted 18yrs
posted by nbg2006
0 comments posted 18yrs posted by nbg2006

First CPLD project

Hi All, I'm doing an internal project for my tiny company and have chosen to use a Xilinx XC9572 and an Atmel ATMEGA324...
3 comments posted 18yrs
posted by gregbdelete
3 comments posted 18yrs posted by gregbdelete

xilinx core generator

Hello, Im new to Xilinx core generator tool and have a very fundamental question. I want to generate a single port RAM...
3 comments posted 18yrs
posted by nairvan
3 comments posted 18yrs posted by nairvan

GTP simulation problems

Hi, since I updated to ISE 10.2 and regenerated my GTPs with coregen I have simulation problems. All output values from...
3 comments posted 18yrs
posted by heinerlitz
3 comments posted 18yrs posted by heinerlitz

Reading FPGA internal memory data

I have some IP output data written in an Altera FPGA memory inside the FPGA. I have two questions here 1) How can I rea...
2 comments posted 18yrs
posted by bajajk
2 comments posted 18yrs posted by bajajk

usb core

is any bug in usb core 2.0 in open cores site.
1 comments posted 18yrs
posted by hmmudassir82
1 comments posted 18yrs posted by hmmudassir82

Mismatch simulation & post sythese results

Hi I am a little bit desperate at the moment. My design is working fine when simulating in with Modelsim. Also the syth...
5 comments posted 18yrs
posted by RobJ
5 comments posted 18yrs posted by RobJ

mean of ddfs

its is direct digital frequency synthesiser
0 comments posted 18yrs
posted by roji.sweet
0 comments posted 18yrs posted by roji.sweet

Using VHDL packages

Hey there, I have asked this question in another forum as well but that forum ha gone into the 2nd page and I am not su...
1 comments posted 18yrs
posted by kamran.wadood
1 comments posted 18yrs posted by kamran.wadood

Why cant XST sythesis this piece of code

Hi When running XST then XST is analysing an entity for ages that contains the following piece of code. if (signal1 = '...
2 comments posted 18yrs
posted by Clemens
2 comments posted 18yrs posted by Clemens

Strange ddr controller bugs.

Hi all: I am meet a very strange ddr controller bugs on board. since system power up. I turn on the ddr controller test...
6 comments posted 18yrs
posted by dadabuley
6 comments posted 18yrs posted by dadabuley

The Code One

http://www.thecodeone.com/vb/index.htm
0 comments posted 18yrs
posted by hesham.hamdy
0 comments posted 18yrs posted by hesham.hamdy

How to simulate baud rate generator?

I've gotten the following code for the baudrate generator from opencores I've created a Test Bench Waveform for it from...
6 comments posted 18yrs
posted by me75
6 comments posted 18yrs posted by me75

ps2 mouse initialization fails

Hi, I tried out 2 mouse modules. Both get stuck in the mouse initialization process. The mouse does not respond. The mo...
4 comments posted 18yrs
posted by me
4 comments posted 18yrs posted by me