Latest threads in Field-Programmable Gate Arrays

The littlest CPU

I may need to add a CPU to a design I am doing. I had rolled my own core once with a 16 bit data path and it worked out...

12 18yrs

gnuarm

12 18yrs gnuarm

Additional Hardware Module with Xilinx MicroBlaze Processor

Hey all, I have a Xilinx Spartan-3E starter board, and I'm implementing a MicroBlaze processor on the FPGA. I would als...

3 18yrs

ray.delvecchio

3 18yrs ray.delvecchio

Virtex-5, DDR2 SRAM, and ISERDES

Is it not recommended to use the ISERDES in the Virtex-5 to perform strobe-based read capture from a DDR2 SRAM (not QDR...

1 18yrs

petersen.curt

1 18yrs petersen.curt

Which FPGA has most ram in a TQFP144 or smaller non-BGA?

Which affordable FPGA has the most dual port block-ram type resources in a TQFP144 or smaller quad flat pack (non-BGA)...

6 18yrs

cs_posting

6 18yrs cs_posting

free video course fpga or asic

Hi every body, I am new to fpga design and I d like to know if there is anyone who knows where I can find free video cou...

1 18yrs

davidbafumba

1 18yrs davidbafumba

ml403_emb_ref_ppc_81.zip problem

My problem is explained here... While creating the new XPS project using Base system Builder: Step 1. New Project->Base...

0 18yrs

nareshgbhat

0 18yrs nareshgbhat

a question about linker map file

Hi, I'm currently working in a POSIX thread management and synchronization library upon xilkernel + (powerpc/microblaze...

2 18yrs

pperogil

2 18yrs pperogil

Problem creating the ML403 project using Xilinx tool

Hi Guys, I am new to Xilinx tools. I am facing some problem while creating the "Base system Builder project" for ML403...

8 18yrs

nareshgbhat

8 18yrs nareshgbhat

verilog code

module chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum); input [159:0] len_tcp; input...

5 18yrs

amboafridi

5 18yrs amboafridi

Free Seminar on Advanced Verification with Aldec’s Riviera-Pro

Free Seminar on Advanced Verification with Aldec=92s Riviera-Pro Given the ever growing complexities of SoC designs, th...

0 18yrs

cvc.training

0 18yrs cvc.training

Need help regarding xupv2p board....

I bought this board so that I can write the whole software using just VHDL. but only info i can find is... to use Power...

1 18yrs

wasifshams

1 18yrs wasifshams

USB 1.1 Function IP Core

If any one use USB 1.1 Function IP Core from opencores site please tell me this core has bugs or not.

1 18yrs

hmmudassir82

1 18yrs hmmudassir82

example of counter for chipscope pro generator

Hi everey one, i am new to chipscope pro,i worked with verilog example of counter,and instantiated vio,icon and ila cor...

1 18yrs

irfan.mohammed

1 18yrs irfan.mohammed

timing constraint - XPower 9.2 problem

Hello, I implemented a design which uses DCM in Virtex-II Pro XC2VP30-7. I have used ISE 9.2. for design implementation...

0 18yrs

ruleevropa

0 18yrs ruleevropa

UTMI

Please tell me if any one know links or have UTMI interfacing core free of bugs in verilog. Please tell me if any one k...

1 18yrs

hmmudassir82

1 18yrs hmmudassir82

Field-Programmable Gate Arrays

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