Field-Programmable Gate Arrays

Virtex-5, DDR2 SRAM, and ISERDES

Is it not recommended to use the ISERDES in the Virtex-5 to perform strobe-based read capture from a DDR2 SRAM (not QDR...

1 comments posted 18yrs

posted by petersen.curt

1 comments posted 18yrs posted by petersen.curt

Which FPGA has most ram in a TQFP144 or smaller non-BGA?

Which affordable FPGA has the most dual port block-ram type resources in a TQFP144 or smaller quad flat pack (non-BGA)...

6 comments posted 18yrs

posted by cs_posting

6 comments posted 18yrs posted by cs_posting

free video course fpga or asic

Hi every body, I am new to fpga design and I d like to know if there is anyone who knows where I can find free video cou...

1 comments posted 18yrs

posted by davidbafumba

1 comments posted 18yrs posted by davidbafumba

ml403_emb_ref_ppc_81.zip problem

My problem is explained here... While creating the new XPS project using Base system Builder: Step 1. New Project->Base...

0 comments posted 18yrs

posted by nareshgbhat

0 comments posted 18yrs posted by nareshgbhat

a question about linker map file

Hi, I'm currently working in a POSIX thread management and synchronization library upon xilkernel + (powerpc/microblaze...

2 comments posted 18yrs

posted by pperogil

2 comments posted 18yrs posted by pperogil

Problem creating the ML403 project using Xilinx tool

Hi Guys, I am new to Xilinx tools. I am facing some problem while creating the "Base system Builder project" for ML403...

8 comments posted 18yrs

posted by nareshgbhat

8 comments posted 18yrs posted by nareshgbhat

verilog code

module chkchk(buff1,len_tcp,src_addr,dest_addr,word,word32,tcplen,prot_tcp,led1,led2,sum); input [159:0] len_tcp; input...

5 comments posted 18yrs

posted by amboafridi

5 comments posted 18yrs posted by amboafridi

Free Seminar on Advanced Verification with Aldec’s Riviera-Pro

Free Seminar on Advanced Verification with Aldec=92s Riviera-Pro Given the ever growing complexities of SoC designs, th...

0 comments posted 18yrs

posted by cvc.training

0 comments posted 18yrs posted by cvc.training

Need help regarding xupv2p board....

I bought this board so that I can write the whole software using just VHDL. but only info i can find is... to use Power...

1 comments posted 18yrs

posted by wasifshams

1 comments posted 18yrs posted by wasifshams

USB 1.1 Function IP Core

If any one use USB 1.1 Function IP Core from opencores site please tell me this core has bugs or not.

1 comments posted 18yrs

posted by hmmudassir82

1 comments posted 18yrs posted by hmmudassir82

example of counter for chipscope pro generator

Hi everey one, i am new to chipscope pro,i worked with verilog example of counter,and instantiated vio,icon and ila cor...

1 comments posted 18yrs

posted by irfan.mohammed

1 comments posted 18yrs posted by irfan.mohammed

timing constraint - XPower 9.2 problem

Hello, I implemented a design which uses DCM in Virtex-II Pro XC2VP30-7. I have used ISE 9.2. for design implementation...

0 comments posted 18yrs

posted by ruleevropa

0 comments posted 18yrs posted by ruleevropa

UTMI

Please tell me if any one know links or have UTMI interfacing core free of bugs in verilog. Please tell me if any one k...

1 comments posted 18yrs

posted by hmmudassir82

1 comments posted 18yrs posted by hmmudassir82

protocol layer

please tell me if any one know or have core of PL (protocol layer) in usb core. please tell me if any one know about PL...

1 comments posted 18yrs

posted by hmmudassir82

1 comments posted 18yrs posted by hmmudassir82

full timing diagram

Please tell any link from i would easily download full timing diagram of all internal block diagrams of usb core. Pleas...

0 comments posted 18yrs

posted by hmmudassir82

0 comments posted 18yrs posted by hmmudassir82