Hi, I have designed a VHDL entity that is a subset of the complete design. I have verified its functionality with a simulation in modelsim and now I want to run it through the xilinx synthesis(XST) and place and route tools to verify it meets timing. This entity is a subset of the complete design, and one of its output ports contains a large number of signals(several thousand). This fails to map since our target FPGA does not have several thousand IO pads. How can I run this sub module through the PAR tools to verify I meet timing?
Here is what I have tried so far:
1) IOB over mapping problem solved by unchecking the XST "add I/O buffers" option. However, the mapper rightfully strips the whole design since there are now no inputs or outputs. I have unsuccessfully tried to use the mapper constraint "SAVE NET FLAG". Despite applying this flag to the inputs and outputs of my submodule, everything still gets stripped.e.g. attribute s: string; attribute s of inputs: signal is "yes";
The map report says: The signal "inputs" is sourceless and has been removed.
I can't understand why the the SAVE NET FLAG constraint is not preserving this signal. Inputs is an array of arrays - perhaps this attribute can't be applied to such a signal ?
Has anyone successfully used SAVE NET FLAG on array of arrays before? What other approaches do folk use to verify timing of a submodule without letting the IOB's affect the result?
(I could create some dummy mux logic to mux the outputs down to a fewer number, so that an achieable number of IOBS are created - But this will distort the timing and logic usage.
Cheers Andrew