Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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The definition of combinatorial process?
The following topic may be one of the longest debate in vhdl group: The debute focus later turns to which is the best way to code: either one sequntial process or two process method, one combinarotial...
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11 years ago
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The definition of comnatorial prcess?
The following topic may be one of the longest debate in vhdl group: The debute focus later turns to which is best way to use one sequential process or two combinarotial process and sequential process....
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11 years ago
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Replacement for XC4005E
We've been using the venerable XC4005E FPGA from Xilinx for many years now in a bunch of products. However the variant we use has now been discontinued, and although we can get sufficient quantities...
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11 years ago
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Modelsim MXE on wine?
I had MXE (Modelsim Xilinx Edition) running successfully under Wine until recently. However, following a lot of changes, I 've just re-installed it, and can't get vsim running. My setup is SL(/RHEL)6,...
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11 years ago
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Call for beta users for Sigasi integration with Altera Quartus
Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We have...
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11 years ago
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What are differences between IBUF and IBUFDS inferred and implemented for differential input signals?
If a design has differential inputs, but the synthesis tool did not infer differential input buffers IBUFDS on Xilinx FPGA for them, IBUFs are inferred instead. What will be the impact to the...
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11 years ago
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RE: ADC problem on spartan3E
can i have ur vhdl code ...wid appreciate it a lot ... thanx in advance. my gmail:
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11 years ago
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Data transfers between MicroBlaze and VHDL
I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am trying to figure out a way that I could output the data from the MicroBlaze to a...
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11 years ago
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Fpga to Asic conversion, firm list and prices.
Maybe is time write more about price and about firm specialized in PGA-to-ASIC replacement. Please, add company name and Your experience with company. Some details about price for sample, some detail...
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11 years ago
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FPGA FIFO MAX data speed
hi, guys: i'm designing a fifo using XILINX FPGA V6. the fifo will be used to transport data between ARM11(OR POWERPC) and TI DSP 6474. i know it's related to the bus clock of both side, but how to...
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11 years ago
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Virtex 4 Cameralink DCM Limitation
I have a cameralink (LVDS SERDES) I'm trying to capture data with using a Virtex 4 mature product. I have ported the XAPP485 deserializer using V4 primitives (slightly different to Spartan3A) and...
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11 years ago
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Reading out LUTM content
Hi all, Following problem: We have an Xilinx Virtix 5, having an implementation running on it. What we want to do, is to read out all the bits (or the state) of the different LUTM cells. At the...
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11 years ago
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FPGA Interconnect
Hi, Here is a question little bit in the internals of the FPGA. I am asking this more out of my curiosity and learning. FPGA LUT typically consists of SRAMs & a Mux at the output. These Muxes need...
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11 years ago
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TCE 1.6
TTA-based Co-design Environment (TCE) v1.6 released --------------------------------------------------- TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors...
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11 years ago
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MPMC does not finish initialization in simulation
Hello Friends, I am working on virtex6. I am trying to debug a problem by simulating in modelsim. But in the simulation I get a different problem. My platform uses DDR3 SDRAM via xilinx's MPMC...
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11 years ago
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