If a design has differential inputs, but the synthesis tool did not infer differential input buffers IBUFDS on Xilinx FPGA for them, IBUFs are inferred instead. What will be the impact to the implementation? Thanks!
differential input buffers IBUFDS on Xilinx FPGA for them, IBUFs are inferred instead. What will be the impact to the implementation? Thanks!
Try it! If Mapping fails, you will have to instantialte them somewhere appropriate.
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Firstly, unless there is some newer info out there, I believe that per the = Xilinx HDL libraries guide, an IBUFDS must be instantiated and cannot be in= ferred. The IBUFDS primitive and its functionality is located up in the I/O= cell and performs the differential to single ended conversion directly.=20
I will presume that your code to infer the differential to single-ended con= version matches the functionality of the IBUFDS logic table in the HDL libr= ary guide. As such with the IBUFs at the I/O cell, the synthesizer will the= n try to replicate the functionality using logic cell(s). A significant per= formance hit will occur do to the delays. These delays will change from ite= ration to iteration as well. Also there will be more susceptibility to glit= ching because it will be more challenging to match the routing of the two s= ignals in and amongst the logic cell fabric.
Regards, Carlton
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