Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Xilinx Xplorer misfunction
Hello, I would like to know if anyone experiences this misfunction in Xplorer tool. I'm using Xilinx ISE 8.2i. When I use Xplorer, it always finds the right implementation parameters on the third run...
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17 years ago
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doubt in verilog coding
hai, i am vishnu i have some doubt regarding verilog coding,i want to have 5 secs delay ,as delays are not synthesziable i have used counter, but my problem is i want to use that counter inside an...
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17 years ago
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DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY
Hi, I'm working on a Virtex4 DDR2 interface based on the direct clocking design from MIG 1.6 (XAPP701). I'm clocking the DDR2 (Micron 1Gb) at 125MHz, so I would expect to see only one edge of DQS...
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17 years ago
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.bit file to VHDL/verilog source code
I am currently working on an old board which have eight FPGA XC3130 on board and i dont have a source code for those FPGA's except for .bit file which was downloaded through VME bus. Currently i am...
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17 years ago
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Welcome to X-Fest 2007
Now that all silly disclaimers have been thoroughly eradicated, come and sign up for X-Fest in a city near you. Whether you are in the U.S. or Canada, in Europe or Isreal, in Asia or Australia or New...
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17 years ago
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SEC:U Problem getting rid of bit latch errors
How do I get rid of bit latch warnings when I compile my code in ISE when I am assigning values to parts of bit vector type signals ? e.g if PROG_FULL
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17 years ago
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Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30)
Hi everybody, I am working with Sundance modules, specifically I have adquired Smt338vp30 which has a Virtex II Pro 30 (ff896-6). I have bought Diamond FPGA too, but I need to work with the PowerPC...
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17 years ago
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Clearing fpga internal memory...
Hi, I have set of registers implemented as internal RAM blocks (in Cyclone FPGA). Is there any way to clear contents of this registers on demand (just like clear signal in D flip-flops)? For answers...
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17 years ago
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Xilinx Netlist
Is there an easy way to get the Xilinx design manager to spit out a netlist for a synthesized VHDL file? Adam
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17 years ago
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Xilinx FPGA, OFFSET OUT AFTER
hi, I want to operate the XILINX Virtex-4 XC4VLX60(Speed -12) at a frequenz of 130 MHz. So i write the following constraints to my UCF(user constraint files). NET "i_clk_adc" PERIOD = 6 ns HIGH 50 %;...
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17 years ago
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interface ad9229 with altera stratix II
can some one give me a hint on how to interface AD9229 a to d converter with stratix II lvds interface? the AD9229 output sample word of 12 bits, however the lvds serdes factor is 10 at the max....
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17 years ago
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Programming XCF from MicroBlaze over JTAG???
Hi, Has anyone had any success in programming a Xilinx XCF using C code in a MicroBlaze over the JTAG ports? Any information appreciated. Thanks!
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17 years ago
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ANNC: Clock Network Implementation Webcast
Lattice is holding a webcast tomorrow Wednesday, March 14, "Revolutionizing Clock Network Implementation." The presenter will be Jim Krebs, from our mixed-signal applications group. Please attend or...
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17 years ago
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qemu+ghdl or uml+ghdl hardware-software cosimulation?
Hi All, I've found a wonderful tool for QEMU+SystemC cosimualtion: as my students are more familiar with VHDL, than with SystemC, I'm looking for a similar solution based on VHDL simulator...
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17 years ago
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PCI - Express
My understanding of the initialising sequence for a PCI-E card is as follows: 1 Detect phase to see if there's a receiver connected 2 Send TS1s 3 Send 1024 TS1 after at least one TS1 has been received...
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17 years ago
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