Field-Programmable Gate Arrays

IOSTANDARD default value in Xilinx UCF-Files?

Hi there! I am wondering what the default IOSTANDARD is on pins for which it is not explicitly assigned in the UCF of t...

5 comments posted 19yrs

posted by t.landschoff

5 comments posted 19yrs posted by t.landschoff

Jam STAPL Player extensions

Hi All, I have sent to alt.sources very "quick & dirty" extensions to Altera's Jam STAPL Player, allowing it to work wi...

4 comments posted 19yrs

posted by wzab

4 comments posted 19yrs posted by wzab

ADC capture with FPGA Spartan3 in Verilg

Hello, This source is a capture the ADC0804 with FPGA Spartan3, Oscillator 50MHz frequency Clk for ADC is 650KHz, sampl...

0 comments posted 19yrs

posted by jrquevedor

0 comments posted 19yrs posted by jrquevedor

FPGA vs. GPP anyone?

Hi, I couldn't find any comparison between FPGA and GPP. I thought I could get some of the expert two-cents on this mat...

6 comments posted 19yrs

posted by yasirmm

6 comments posted 19yrs posted by yasirmm

CFP : FPL 2007 (Submission deadline extended to 25th of March)

******************************************************************************* 2007 International Conference on Field...

0 comments posted 19yrs

posted by m8pple

0 comments posted 19yrs posted by m8pple

how to transform Arun's LDPC code to max-product (Min-sum)?

how to transform Arun's LDPC code to max-product (Min-sum)? comp.dsp LDPC Advice would be appreciated on how to transfo...

2 comments posted 19yrs

posted by 1888

2 comments posted 19yrs posted by 1888

How to find pcore directory from within EDK TCL script?

I am working on TCL scripts that go with EDK pcores that I am developing. The MPD file allows me to specify that I want...

0 comments posted 19yrs

posted by jhmccaskill

0 comments posted 19yrs posted by jhmccaskill

Eval board advice

Howdy, I'm looking at Xilinx FPGA boards in the $300 range. In a grad school course I worked with a Memec Virtex II-Pro...

8 comments posted 19yrs

posted by odofile

8 comments posted 19yrs posted by odofile

XPower crashes....

Hi, I do a post place and route simulation using modelsim. To estimate the power I generate dump.vcd file during simula...

2 comments posted 19yrs

posted by amirhossein.gholamipour

2 comments posted 19yrs posted by amirhossein.gholamipour

Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?

Hi, In my many projects, some signals have both positive reference and negative reference, does it cause an additional...

6 comments posted 19yrs

posted by wtxwtx

6 comments posted 19yrs posted by wtxwtx

Xilinx XST 9.1, Verilog 2-D arrays, always @*

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* block. Here's a (perhaps poor) example: reg si...

10 comments posted 19yrs

posted by ancd

10 comments posted 19yrs posted by ancd

Systemverilog preprocessor allow "..."?

ANSI-C preprocessor supports a 'wildcard' ... #include #define _NOISY_PRINTF( ... ) printf( ... ) #define _QUIET_PRINTF...

1 comments posted 19yrs

posted by ancd

1 comments posted 19yrs posted by ancd

What official function should I call to genertate a sum of products in VHDL

Hi, What official functions should I call to genertate a sum of products in VHDL? S(...)

2 comments posted 19yrs

posted by wtxwtx

2 comments posted 19yrs posted by wtxwtx

Xilinx ISE support for dual/quad core CPUs?

Hi, I'm about to buy a new workstation for FPGA development and I'm hesitating between a Core 2 Extreme @ 2.93 GHz (X68...

16 comments posted 19yrs

posted by prdubois

16 comments posted 19yrs posted by prdubois

Virtex5 LXT and synthesis..

Folks, I need to do a trial synthesis to see if one of our ASIC design module will run at speed (~312.5Mhz) in Xilinx V...

4 comments posted 19yrs

posted by cshroff

4 comments posted 19yrs posted by cshroff