Latest threads in Field-Programmable Gate Arrays

direct access on opb_emc

I have a usb phy chip sitting on my opb_emc. I always have to use XIo_Out and XIo_In to access. Direct read/write to th...

1 19yrs

cepope

1 19yrs cepope

QuickSilver's ACM architecture

I am seeking information on QuickSilver Technology's "Adaptive Computing System" framework. Their infrastructure sounde...

0 19yrs

anneatkinson

0 19yrs anneatkinson

IOSTANDARD default value in Xilinx UCF-Files?

Hi there! I am wondering what the default IOSTANDARD is on pins for which it is not explicitly assigned in the UCF of t...

5 19yrs

t.landschoff

5 19yrs t.landschoff

Jam STAPL Player extensions

Hi All, I have sent to alt.sources very "quick & dirty" extensions to Altera's Jam STAPL Player, allowing it to work wi...

4 19yrs

wzab

4 19yrs wzab

ADC capture with FPGA Spartan3 in Verilg

Hello, This source is a capture the ADC0804 with FPGA Spartan3, Oscillator 50MHz frequency Clk for ADC is 650KHz, sampl...

0 19yrs

jrquevedor

0 19yrs jrquevedor

FPGA vs. GPP anyone?

Hi, I couldn't find any comparison between FPGA and GPP. I thought I could get some of the expert two-cents on this mat...

6 19yrs

yasirmm

6 19yrs yasirmm

CFP : FPL 2007 (Submission deadline extended to 25th of March)

******************************************************************************* 2007 International Conference on Field...

0 19yrs

m8pple

0 19yrs m8pple

how to transform Arun's LDPC code to max-product (Min-sum)?

how to transform Arun's LDPC code to max-product (Min-sum)? comp.dsp LDPC Advice would be appreciated on how to transfo...

2 19yrs

1888

2 19yrs 1888

How to find pcore directory from within EDK TCL script?

I am working on TCL scripts that go with EDK pcores that I am developing. The MPD file allows me to specify that I want...

0 19yrs

jhmccaskill

0 19yrs jhmccaskill

Eval board advice

Howdy, I'm looking at Xilinx FPGA boards in the $300 range. In a grad school course I worked with a Memec Virtex II-Pro...

8 19yrs

odofile

8 19yrs odofile

XPower crashes....

Hi, I do a post place and route simulation using modelsim. To estimate the power I generate dump.vcd file during simula...

2 19yrs

amirhossein.gholamipour

2 19yrs amirhossein.gholamipour

Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?

Hi, In my many projects, some signals have both positive reference and negative reference, does it cause an additional...

6 19yrs

wtxwtx

6 19yrs wtxwtx

Xilinx XST 9.1, Verilog 2-D arrays, always @*

I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* block. Here's a (perhaps poor) example: reg si...

10 19yrs

ancd

10 19yrs ancd

Systemverilog preprocessor allow "..."?

ANSI-C preprocessor supports a 'wildcard' ... #include #define _NOISY_PRINTF( ... ) printf( ... ) #define _QUIET_PRINTF...

1 19yrs

ancd

1 19yrs ancd

What official function should I call to genertate a sum of products in VHDL

Hi, What official functions should I call to genertate a sum of products in VHDL? S(...)

2 19yrs

wtxwtx

2 19yrs wtxwtx

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