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DDR2: Why do I see two edges of a 125MHz DQS on the IDELAY

Hi,

I'm working on a Virtex4 DDR2 interface based on the direct clocking design from MIG 1.6 (XAPP701). I'm clocking the DDR2 (Micron 1Gb) at

125MHz, so I would expect to see only one edge of DQS during calibration using the IDELAY. However, from chipscope I see two edges only approx 900ps apart. I notice there are lots of IDELAY queries on here... can anyone explain what is going on? The design uses an IDELAYCTRL clocked at 200MHz from a DCM CLKFX with a 50MHz clkin.

The result is intermittant read errors, I suspect since the calibrated data delay is totally wrong...

Many thanks,

Rob

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rob.dimond
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Hi,

I thought I would answer my own question in case anyone has a similar problem in the future. I wasn't resetting the IDELAYCTRL properly. The reset signal in the

200MHz clock domain is derived from the same reset used for the DCM itself, so is never asserted. According to the V4 user guide the behavior is 'unpredictable' without a reset... now I know what this means.

Interestingly, some other reset signals in the MIG design look to have the same problem...

Rob

Reply to
Rob Dimond

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