Clearing fpga internal memory...

Just like flops? Absolutely not.

No memories come with resets. Not DDR SDRAMs, not SRAMs, not BlockRAMs, not distributed CLB SelectRAMs, not TriMatrix Memory.

To clear the memory you either need to write every address or keep a separate bunch of registers as tags for each entry to label them as "not updated" in which case the value should be forced zero when read (at which time the flag is cleared). Some people call these "dirty bits" to keep track of which entries provides clean data and which don't.

People who do fancy code can even have dirty bit registers to track a dirty bit memory array for those larger memory tasks.

The basic idea is:

Clear: Set all dirty bits. Read: value

"Sylvain Munaut" wrote in message news: snipped-for-privacy@youknowwhattodo.com...

Thanks for the clarification - my mistake. You have things right, indeed.

I remember wondering some years ago (in the 8080 days) if SRAM tended to power up to the same state. It seemed that the screen image on power up, before the software cleared the screen, tended to be similar. While a clear would be expensive, designing memory cells, either SRAM or DRAM, to power up in a certain state might not be as expensive. I don't know that anyone has tried, though.

I also remember discussions about EPROMs that erase to either 0 or 1, and which processors have opcode X'00' as NOOP.

-- glen

DRAMs do not guarantee any specific power-up value but because they are built on femtofarad capacitors and somewhat leaky silicon, they should have a tendency to power-up mostly cleared. For SRAMs, I suspect results would indicate that they tend to power up with a specific device-unique pattern dictated by either the leakiest or strongest transistor in each bit and, given low-leakage transistors, it is not inconceivable that they may power-up biased towards their former power-on state.

Guaranteeing that an SRAM cell will always power-up cleared (without Peter's clear input and the extra cell transistors) would require making the SRAM cell leaky by design and that would be really bad for static power usage. While this "solution" does not cost any surface area, it would cost some power and decrease manufacturability: devices that would fail to power-up with all memories cleared but are in otherwise perfect working order would be out-of-spec and have to be either scrapped or sold as "dirty power-up" parts that consume something like 1W extra static power for no reason. 1W may be nothing to you but some people are working on low-power FPGA applications and would not dare touch such parts with a broomstick.

There aren't many applications where garbage memory content at power-up is a major issue and for the few cases where it may be so, there usually are a few simple work-arounds like having one reset for memories that need clearing and a second for everything else that gets stretched until the memory clearing processes are done.

EPROMs work by trapping a charge in the matrix's isolated gate transistors. The UV exposure increases the cells' leakage current to clear the device while programming is done by "controlled failure" of the isolated gate to program 1s, this is why EPROMs have somewhat low reprogramming endurance.

Xilinx BRAMs do initialize in a known state on FPGA configuration. The memory can be set to specific contents, or will default to all zero.

True, but device reprogramming happens only once at power-up unless triggered by other means afterwards. Since the OP was about clearing memory "on-demand", none of those power-up-specific details are relevant though.

Right, I realize that. I made this comment because someone brought up the power-up state of commodity memories.

Yes, I was considering more than 15 years ago (when the 8080 was a popular processor).

I believe the thought at the time was an initialized RAM that would power up with some useful data, which could then be changed.

-- glen