Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Exciting openings for Standard Cell libraries/Memory designer in a fortune 50 organisation
Hi All, This is Nitin Gupta from Itprogress. We are a Noida based executive search firm specializing in targetted search of professionals. We are looking for Sr.Engineers/Managers- Standard Cell...
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16 years ago
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Need suggestion for my project
I am now preparing the project: encryption data stored in the SATA disk. I want to realize a device placed between the pc and SATA disk as following: PC SATA controller FPGA board SATA disk I planed...
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16 years ago
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xilinx plb_ddr to self refresh mode
Can anyone tell me how to command the plb_ddr core to put my external ddr sdram into self refresh mode? Thanks, Clark
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16 years ago
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new to the group
hi all, i am new to this group and i am beginner in this FPGA field so i need ur help to find some material regarding FPGA i hope u people can help me out thank u
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16 years ago
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DSP design into FPGA
hi all.. Is it possible to import the design which is converted into a file by Altera DSP builder into SOPC builder. i have converted it into a *.ptf file but was unable to import into the design. can...
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16 years ago
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how to test the FPGA on the board
hi all I have to test an fpga on a customised board could anybody suggest me the methods for this archana
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16 years ago
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Single Ended signal in sync with V5 GTP
I need to generate a signle ended signal possibly using the V5 Select I/O pin that is synchronous to one of the GTP output running at 400Mbps. The sigle ended signal needs to be 1.5V Push-pull type. I...
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16 years ago
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bidirectional pin
Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that in VHDL there is keyword "inout" when defining port, but I don't know what...
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16 years ago
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FPGA accelerator service
Hi. I'm looking for a company who implement various algorithms using FPGA accelerators. Who can take part of some software code and rework it completely to make working FPGA accelerator in form,...
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16 years ago
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OpenSPARC
Hi. Does somebody have a real success with burning OpenSPARC to FPGA?
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16 years ago
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bare bone PCI cards with FPGAs
I have a certain demand on processing digital data with a PC and thought about to do this with an FPGA/PC. What would be fine was a PCI compatible card with an FPGA on it which could be extended to my...
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16 years ago
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Confused about my behavioral simulation under ISE 9.1
Gang I created a module, downloaded it to my dev board and ran it. The LED's changed as I expected. I decided to run a behavioral simulation to prove to myself that signals were changing the way I...
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16 years ago
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Area report
I am reading some papers about algorthms implementation. I noticed they like to compare the synthesis area of the fixed-point implementation. I wander where they find the area report for the...
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16 years ago
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mb-gdb: problem simulating memory mapped i/o devices
Hello, I'm trying to simulate a C program in MB-GDB but I get trouble when trying to simulate memory based I/O devices. I'm not using Microblaze but a improved Openfire core (same ISA) so microblaze...
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16 years ago
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xps error never seen before: google reveals nothing; help!
(reposting with catchier subject line and some changes...) Hi, We are trying to run the "Virtex4_PPC_Example_9_1" example program from EDK9.1.2 that has TestInterrupt.c routine (timer interrupt...
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16 years ago
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