Latest threads in Field-Programmable Gate Arrays

Exciting openings for Standard Cell libraries/Memory designer in a fortune 50 organisation

Hi All, This is Nitin Gupta from Itprogress. We are a Noida based executive search firm specializing in targetted searc...

0 19yrs

nitin74_gupta

0 19yrs nitin74_gupta

Need suggestion for my project

I am now preparing the project: encryption data stored in the SATA disk. I want to realize a device placed between the...

7 19yrs

xing.starwill

7 19yrs xing.starwill

xilinx plb_ddr to self refresh mode

Can anyone tell me how to command the plb_ddr core to put my external ddr sdram into self refresh mode? Thanks, Clark

2 19yrs

cepope

2 19yrs cepope

new to the group

hi all, i am new to this group and i am beginner in this FPGA field so i need ur help to find some material regarding FP...

4 19yrs

jitendrakumarpothuru

4 19yrs jitendrakumarpothuru

DSP design into FPGA

hi all.. Is it possible to import the design which is converted into a class.ptf file by Altera DSP builder into SOPC b...

0 19yrs

srimankk

0 19yrs srimankk

how to test the FPGA on the board

hi all I have to test an fpga on a customised board could anybody suggest me the methods for this archana

1 19yrs

ramaarchana

1 19yrs ramaarchana

Single Ended signal in sync with V5 GTP

I need to generate a signle ended signal possibly using the V5 Select I/O pin that is synchronous to one of the GTP out...

5 19yrs

bidirectional pin

Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that i...

8 19yrs

Zorjak

8 19yrs Zorjak

FPGA accelerator service

Hi. I'm looking for a company who implement various algorithms using FPGA accelerators. Who can take part of some softw...

1 19yrs

drop669

1 19yrs drop669

OpenSPARC

Hi. Does somebody have a real success with burning OpenSPARC to FPGA?

3 19yrs

drop669

3 19yrs drop669

bare bone PCI cards with FPGAs

I have a certain demand on processing digital data with a PC and thought about to do this with an FPGA/PC. What would b...

1 19yrs

fpgaengineerfrankfurt

1 19yrs fpgaengineerfrankfurt

Confused about my behavioral simulation under ISE 9.1

Gang I created a module, downloaded it to my dev board and ran it. The LED's changed as I expected. I decided to run a...

2 19yrs

bob.zigon

2 19yrs bob.zigon

Area report

I am reading some papers about algorthms implementation. I noticed they like to compare the synthesis area of the fixed...

3 19yrs

threeinchnail

3 19yrs threeinchnail

mb-gdb: problem simulating memory mapped i/o devices

Hello, I'm trying to simulate a C program in MB-GDB but I get trouble when trying to simulate memory based I/O devices....

0 19yrs

manuel-lozano

0 19yrs manuel-lozano

xps error never seen before: google reveals nothing; help!

(reposting with catchier subject line and some changes...) Hi, We are trying to run the "Virtex4_PPC_Example_9_1" examp...

4 19yrs

mouli1982

4 19yrs mouli1982

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