Field-Programmable Gate Arrays

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xilinx plb_ddr to self refresh mode

Can anyone tell me how to command the plb_ddr core to put my external ddr sdram into self refresh mode? Thanks, Clark
2 comments posted 19yrs
posted by cepope
2 comments posted 19yrs posted by cepope

new to the group

hi all, i am new to this group and i am beginner in this FPGA field so i need ur help to find some material regarding FP...
4 comments posted 19yrs
posted by jitendrakumarpothuru
4 comments posted 19yrs posted by jitendrakumarpothuru

DSP design into FPGA

hi all.. Is it possible to import the design which is converted into a class.ptf file by Altera DSP builder into SOPC b...
0 comments posted 19yrs
posted by srimankk
0 comments posted 19yrs posted by srimankk

how to test the FPGA on the board

hi all I have to test an fpga on a customised board could anybody suggest me the methods for this archana
1 comments posted 19yrs
posted by ramaarchana
1 comments posted 19yrs posted by ramaarchana

Single Ended signal in sync with V5 GTP

I need to generate a signle ended signal possibly using the V5 Select I/O pin that is synchronous to one of the GTP out...
5 comments posted 19yrs
posted by
5 comments posted 19yrs posted by

bidirectional pin

Hi, I start work on some project involving FPGA and I have to define port as bidirectional (inut-output). I know that i...
8 comments posted 19yrs
posted by Zorjak
8 comments posted 19yrs posted by Zorjak

FPGA accelerator service

Hi. I'm looking for a company who implement various algorithms using FPGA accelerators. Who can take part of some softw...
1 comments posted 19yrs
posted by drop669
1 comments posted 19yrs posted by drop669

OpenSPARC

Hi. Does somebody have a real success with burning OpenSPARC to FPGA?
3 comments posted 19yrs
posted by drop669
3 comments posted 19yrs posted by drop669

bare bone PCI cards with FPGAs

I have a certain demand on processing digital data with a PC and thought about to do this with an FPGA/PC. What would b...
1 comments posted 19yrs
posted by fpgaengineerfrankfurt
1 comments posted 19yrs posted by fpgaengineerfrankfurt

Area report

I am reading some papers about algorthms implementation. I noticed they like to compare the synthesis area of the fixed...
3 comments posted 19yrs
posted by threeinchnail
3 comments posted 19yrs posted by threeinchnail

mb-gdb: problem simulating memory mapped i/o devices

Hello, I'm trying to simulate a C program in MB-GDB but I get trouble when trying to simulate memory based I/O devices....
0 comments posted 19yrs
posted by manuel-lozano
0 comments posted 19yrs posted by manuel-lozano

Xilinx XC4VLX40-10FFG1148C - Available New

I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not ope...
0 comments posted 19yrs
posted by mvarman
0 comments posted 19yrs posted by mvarman

SDR SDRAM controller for Xilinx Spartan-3E

Hello, I would like to utilize a controller for a SINGLE data rate SDRAM (Micron MT48LC16M16A2TG-75, to be specific). I...
15 comments posted 19yrs
posted by eli
15 comments posted 19yrs posted by eli