Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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reconfigurable, modular design and clock signals - Question
Hello, I have a question about the modular design flow for partial reconfiguration. I created a small pr demo using xilinx modular design flow for a virtex2pro fpga. It consists of 2 static parts with...
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16 years ago
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Drigmorn1 - The Cheapest FPGA Development Board???
We have been promising this for a while and I am finally pleased to show first images and details of Drigmorn1 here We are aiming this to be the cheapest develoment board out there so if know any...
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16 years ago
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why do i see negative clock hold time
hello when i look at the timing report of my fpga i see that the why do i see negative clock hold time of my input pins is NEGATIVE Thold= -5ns i dont understand why thanks for the help
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16 years ago
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Mixed language design
I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only about ten signals on the interface). (For the curious, it performs a function for...
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16 years ago
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can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation
I recently upgraded from a Centos 4.5 x86_64 (Red Hat Enterprise 4 Update 5) installation to Centos 5.1. I reinstalled the O/S from scratch. When I try to install Xilinx ISE 9.2 Foundation...
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16 years ago
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Need help with Altera .pof format!
Hello! I have made a serial firmware downloader for the EPC4 device, and have a couple of questions. After looking at different .pof files, it looks like the file is made up of (on the epc4):...
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16 years ago
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"simultaneously switching output"
Im new to FPGA, so id like to ask what is "simultaneously switching output ? Is it connected with noise problem which comes from switching ? How to prevent it ? thx for all answers MWJ
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16 years ago
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RAM32X1D and Virtex-5
Hi All, The Virtex-5 user guide lists RAM32X1D as a distributed RAM primitive, however this primitive is not listed in the libraries guide. Does anyone know whether this primitive is supported or not?...
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16 years ago
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Spartan 3e and SDRAM
I'm planning to use Spartan 3e and SDRAM for a product - sort of a simple video "card" for an embedded CPU system. I got myself the Spartan 3e STARTER kit and I'm trying to use the SDRAM on board....
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16 years ago
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BUFGCE
HI I have a question about the use of an BUFGCE in a xilinx design. (currently using a virtex 4). when i enable the buffer it seems to loose one clock cycle. 1 2 3 4 ___ ___ ___ ___ ___ CLK_IN __|...
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16 years ago
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clock cycle per Instructions
Hi all, I am trying to calculate clock cycles per instructions by running the test cases and monitoring the waveforms. I am confused to calculate the cycles for memory and IO related instructions......
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16 years ago
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converting verilog to vhdl
Hello I am trying to convert the following code to vhdl assign Q = (rst==0)?Q_int:1'do; How do i convert this to vhdl? I have to use a concurrent statement as this statement is not in the always block...
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16 years ago
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clock lines
Hi, I am reading the Spartan3E user guide and I had a question regarding the clock infrastructure. It says that there are 8 "quadrant clock lines" A - H. Does that mean that my code can ONLY have...
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16 years ago
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Can't get Quartus to Infer Dual Port Ram for Stratix2GX
How do I get Quartus to infer a dual port RAM? I've tried a couple of coding styles neither worked. I've also tried putting a /* syn_ramstyle = "M4K" */ on the module statement and on the ram...
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16 years ago
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UK FPGA supplier
Try in Oxford.
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16 years ago
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