BUFGCE

It was my impression that this glitchless device was very well documented. Have you read up on the BUFCE or did you just come straight here when it didn't look like the AND gate you expected?

The BUFCE will guarantee the output doesn't produce a runt pulse by using some elegant asynchronous handshaking. Thanks, Peter!

While my mind tends to settle back on the BUFGMUX which has stronger needs, the control for the BUFCE *may* simply register the enable control on the falling edge of CLK_IN so the CLK_OUT is guaranteed to be a full high pulse.

well no i didn't come stright here. i looked it up in the virtex datasheet but as far as i understood (and read) it doesn't register the enable on the falling edge. although it appears to be like that when i look at the simulation... but if i compare it with the timing diagramm from the datasheet it looks different.. in that timing diagramm the clock output is working immediately after the enable (even if there is no falling edge)

thanks

The BUFGCE and BUFGMUX are the same element:

hmm i'm still struggling with the clock gating. i looked it up in the datasheet again :

and on page 32 there is the timing diagramm for the bufgce. it appears to me that if the enable signal goes high the next clock edge should bee seen on the output. (if the enable signal is soon enough before that edge of course). but in my simulation it is not. any ideas what i'm doing wrong here or don't understand ?

I'd suggest calling the support hotline. I suspect that the lone timing diagram you refer to is incorrect whereas the simulation (and real hardware) give different results than what that diagram communicates. If the user guide's information is valid, it's only valid because of an option set in the hardware which isn't the normal way the BUFCE operates. It's probable that the user guide documentation is just wrong and needs to be changed: something that can be effected by opening a case.