Latest threads in Field-Programmable Gate Arrays

reconfigurable, modular design and clock signals - Question

Hello, I have a question about the modular design flow for partial reconfiguration. I created a small pr demo using xil...

4 18yrs

l.s.rockfan

4 18yrs l.s.rockfan

Drigmorn1 - The Cheapest FPGA Development Board???

We have been promising this for a while and I am finally pleased to show first images and details of Drigmorn1 here htt...

9 18yrs

g1

9 18yrs g1

why do i see negative clock hold time

hello when i look at the timing report of my fpga i see that the why do i see negative clock hold time of my input pins...

2 18yrs

MADORIG

2 18yrs MADORIG

Mixed language design

I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only...

8 18yrs

MikeShepherd564

8 18yrs MikeShepherd564

can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation

I recently upgraded from a Centos 4.5 x86_64 (Red Hat Enterprise 4 Update 5) installation to Centos 5.1. I reinstalled...

2 18yrs

helpme

2 18yrs helpme

Need help with Altera .pof format!

Hello! I have made a serial firmware downloader for the EPC4 device, and have a couple of questions. After looking at d...

0 18yrs

larstore

0 18yrs larstore

"simultaneously switching output"

Im new to FPGA, so id like to ask what is "simultaneously switching output ? Is it connected with noise problem which co...

3 18yrs

wojjed

3 18yrs wojjed

RAM32X1D and Virtex-5

Hi All, The Virtex-5 user guide lists RAM32X1D as a distributed RAM primitive, however this primitive is not listed in...

0 18yrs

BertyBooster

0 18yrs BertyBooster

Spartan 3e and SDRAM

I'm planning to use Spartan 3e and SDRAM for a product - sort of a simple video "card" for an embedded CPU system. I go...

4 18yrs

alexf

4 18yrs alexf

BUFGCE

HI I have a question about the use of an BUFGCE in a xilinx design. (currently using a virtex 4). when i enable the buf...

5 18yrs

u_stadler

5 18yrs u_stadler

clock cycle per Instructions

Hi all, I am trying to calculate clock cycles per instructions by running the test cases and monitoring the waveforms....

1 18yrs

fazulu.vlsi

1 18yrs fazulu.vlsi

converting verilog to vhdl

Hello I am trying to convert the following code to vhdl assign Q = (rst==0)?Q_int:1'do; How do i convert this to vhdl?...

13 18yrs

thakkar.anuja

13 18yrs thakkar.anuja

clock lines

Hi, I am reading the Spartan3E user guide and I had a question regarding the clock infrastructure. It says that there a...

5 18yrs

axr0284

5 18yrs axr0284

Can't get Quartus to Infer Dual Port Ram for Stratix2GX

How do I get Quartus to infer a dual port RAM? I've tried a couple of coding styles neither worked. I've also tried put...

5 18yrs

schvantzkopf

5 18yrs schvantzkopf

UK FPGA supplier

Try www.orangetreetech.com in Oxford.

0 18yrs

dbeck88

0 18yrs dbeck88

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