Field-Programmable Gate Arrays

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why do i see negative clock hold time

hello when i look at the timing report of my fpga i see that the why do i see negative clock hold time of my input pins...
2 comments posted 18yrs
posted by MADORIG
2 comments posted 18yrs posted by MADORIG

Mixed language design

I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only...
8 comments posted 18yrs
posted by MikeShepherd564
8 comments posted 18yrs posted by MikeShepherd564

Need help with Altera .pof format!

Hello! I have made a serial firmware downloader for the EPC4 device, and have a couple of questions. After looking at d...
0 comments posted 18yrs
posted by larstore
0 comments posted 18yrs posted by larstore

"simultaneously switching output"

Im new to FPGA, so id like to ask what is "simultaneously switching output ? Is it connected with noise problem which co...
3 comments posted 18yrs
posted by wojjed
3 comments posted 18yrs posted by wojjed

RAM32X1D and Virtex-5

Hi All, The Virtex-5 user guide lists RAM32X1D as a distributed RAM primitive, however this primitive is not listed in...
0 comments posted 18yrs
posted by BertyBooster
0 comments posted 18yrs posted by BertyBooster

Spartan 3e and SDRAM

I'm planning to use Spartan 3e and SDRAM for a product - sort of a simple video "card" for an embedded CPU system. I go...
4 comments posted 18yrs
posted by alexf
4 comments posted 18yrs posted by alexf

BUFGCE

HI I have a question about the use of an BUFGCE in a xilinx design. (currently using a virtex 4). when i enable the buf...
5 comments posted 18yrs
posted by u_stadler
5 comments posted 18yrs posted by u_stadler

clock cycle per Instructions

Hi all, I am trying to calculate clock cycles per instructions by running the test cases and monitoring the waveforms....
1 comments posted 18yrs
posted by fazulu.vlsi
1 comments posted 18yrs posted by fazulu.vlsi

converting verilog to vhdl

Hello I am trying to convert the following code to vhdl assign Q = (rst==0)?Q_int:1'do; How do i convert this to vhdl?...
13 comments posted 18yrs
posted by thakkar.anuja
13 comments posted 18yrs posted by thakkar.anuja

clock lines

Hi, I am reading the Spartan3E user guide and I had a question regarding the clock infrastructure. It says that there a...
5 comments posted 18yrs
posted by axr0284
5 comments posted 18yrs posted by axr0284

UK FPGA supplier

Try www.orangetreetech.com in Oxford.
0 comments posted 18yrs
posted by dbeck88
0 comments posted 18yrs posted by dbeck88

XILINX XABEL

Hi, Is there anyone that has XABEL for Sun available, due to some internal mess we have managed to loose our old XABEL...
2 comments posted 18yrs
posted by michael_laajanen
2 comments posted 18yrs posted by michael_laajanen

EDK does not find Modelsim

Hi, I want to launch Modelsim from within Xilinx EDK. I have the correct versions installed, the ISE recognizes Modelsi...
1 comments posted 18yrs
posted by timo.g
1 comments posted 18yrs posted by timo.g