Can't get Quartus to Infer Dual Port Ram for Stratix2GX

I finally gave up on inferring RAM blocks - the synthesizer is just too fiddle. However, if you still want to try, use the templates. You'll find them under the Edit menu.

Good luck, Tommy

I managed to make it work but it's incredibly sensitive. The two ports have to be in different always blocks even though they share the same clock. Also there doesn't seem to be a way to put a clock enable on the read. I put in a work around that saves the address in a register and then selects it if there is no clock enable but that's a kludge that wastes logic and will slow down the address path. Altera needs to fix this.

assign a_adr = a_ce ? a_addr : a_indx; assign b_adr = b_ce ? b_addr : b_indx; always@(posedge sysclk) begin if(a_wrt && a_ce) begin ram[a_adr]

is there a reason why not use the mega wizzard? I have a Stratix II GX running with various DP-RAMs.

I suspect that the O/P was trying to avoid having technology-dependent RT files and hence aid reuse. However, it looks like the synthesis tools wil thwart his worthy aim!

You are absolutely right. I try to make my cores as technology independent as possible. I have customers using them in both Xilinx and Altera FPGAs as well as in ASICs. Even if you are staying with one vendor you still want portable code if possible because the vendors make major changes in their architectures. This particular design was done for the Virtex2P, migrated to the Virtex4FX and then to the Stratix2GX. It will eventually be in the Virtex5FX and the next Stratix than has SerDes (I don't know if that will be Stratix3GX or Stratix4GX, I've heard that Altera is skipping the Stratix3GX). Having to directly instantiate components complicates things. It also makes designs messier because you need a couple of levels of wrappers, the wrapper that the wizard generates and a wrapper around that which makes it generic. It also means that you have to do additional simulation because you have to run your testbench on each variant.