Latest threads in Field-Programmable Gate Arrays

Trouble with instantiation of RPM core - RLOCs are not obeyed

Hello, I have successfully made an RPM core using the floorplanner "Write RPM to UCF" feature and created a core.ngc an...

0 18yrs

jonlassen.news

0 18yrs jonlassen.news

Different synthesis report between ISE-xst and EDK-xst

Hi all! I've really trouble to implement a simple application on a XUP Virtex- II Board using the PPC and PLB as Interf...

1 18yrs

sven.artz

1 18yrs sven.artz

Registrations open for VLSI Conference 2008 in Hyderabad, India

The '21st International Conference on VLSI Design and the 7th International Conference on Embedded Systems' are being h...

0 18yrs

gdbansal

0 18yrs gdbansal

PCI Parallel port card for JTAG / programming?

Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and pro...

5 18yrs

xjjzdv402

5 18yrs xjjzdv402

GAL16V8

Hello, I have a simple project in mind and have some GAL16V8 PLD's knocking around, could anyone suggest a design suite...

4 18yrs

martincharlwood

4 18yrs martincharlwood

Xilinx ise 9.2i clean up project files

Just recently an error/bug arises in ISE when i go to synthesise a design. The synthesis will just error without any tr...

8 18yrs

godzillalad

8 18yrs godzillalad

ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date

Hi I just tried to initialise the JTAG Scan when I get the following error: Info: impact:501 - 1 Added Device xc95144xl...

0 18yrs

Mike

0 18yrs Mike

keep_hierarchy attribute equivalent for Lattice/Synplicity?

I was wondering if anyone could help me figure out one thing that is holding us up for porting some Verilog code that w...

5 18yrs

theosib

5 18yrs theosib

Questions about Timing closure Floorplan and individual timing constraints

Hi everyone: Is there any manual about the symbols in Timing closure Floorplan, Quartu II? I do not find a detailed des...

0 18yrs

dechenxu

0 18yrs dechenxu

Net hierarchy with Xilinx 9.1

Hi, I ran into a small problem while trying to use a UCF file created for ISE 8.2 within EDK 9.1. I had a few INSTs and...

2 18yrs

louis.dupont

2 18yrs louis.dupont

Xilinx EDK simulation

Hi, I've been able to run a simulation of a PPC405 system example with ModelsimPE if the executable elf file fits into...

1 18yrs

cwoodring

1 18yrs cwoodring

What to look for when synthesising verilog code originally written for ASIC to FPGA?

Regarding to necessary changes to verilog code, am I missing something, 1. caches and memories, replacing using FPGA bl...

1 18yrs

wei.wang.cantab

1 18yrs wei.wang.cantab

Drigmorn1 More Info

Some more information on our new low cost Spartan-3E development board Drigmorn1. First FAQ and reference design materi...

0 18yrs

g1

0 18yrs g1

DDS generator with interpolated samples for Spartan3E development board

I've read the Wikipedia article about Direct Digital Synthesis ( http://en.wikipedia.org/wiki/Direct_digital_synthesis...

27 18yrs

fb

27 18yrs fb

problem interfacing AD9510 via serial controller

Hi all, I'm trying to implement an analoge capturing project using Xilinx sx55 fpga and AD9510 as ADC. But I'v difficul...

1 18yrs

naliali

1 18yrs naliali

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