Field-Programmable Gate Arrays

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PCI Parallel port card for JTAG / programming?

Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and pro...
5 comments posted 18yrs
posted by xjjzdv402
5 comments posted 18yrs posted by xjjzdv402

GAL16V8

Hello, I have a simple project in mind and have some GAL16V8 PLD's knocking around, could anyone suggest a design suite...
4 comments posted 18yrs
posted by martincharlwood
4 comments posted 18yrs posted by martincharlwood

Xilinx ise 9.2i clean up project files

Just recently an error/bug arises in ISE when i go to synthesise a design. The synthesis will just error without any tr...
8 comments posted 18yrs
posted by godzillalad
8 comments posted 18yrs posted by godzillalad

Net hierarchy with Xilinx 9.1

Hi, I ran into a small problem while trying to use a UCF file created for ISE 8.2 within EDK 9.1. I had a few INSTs and...
2 comments posted 18yrs
posted by louis.dupont
2 comments posted 18yrs posted by louis.dupont

Xilinx EDK simulation

Hi, I've been able to run a simulation of a PPC405 system example with ModelsimPE if the executable elf file fits into...
1 comments posted 18yrs
posted by cwoodring
1 comments posted 18yrs posted by cwoodring

Drigmorn1 More Info

Some more information on our new low cost Spartan-3E development board Drigmorn1. First FAQ and reference design materi...
0 comments posted 18yrs
posted by g1
0 comments posted 18yrs posted by g1

problem interfacing AD9510 via serial controller

Hi all, I'm trying to implement an analoge capturing project using Xilinx sx55 fpga and AD9510 as ADC. But I'v difficul...
1 comments posted 18yrs
posted by naliali
1 comments posted 18yrs posted by naliali

the FPGA gate way

hi all: Recently i'm doing the FPGA gate way. I have a smsc netcard(MAC +PHY). My main task is the gateway can receive...
0 comments posted 18yrs
posted by guochenglv
0 comments posted 18yrs posted by guochenglv