Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Keeping Xilinx tool from Optimizing out Debugging signals
There is a signal that I need to trigger Chipscope on it for debugging purposes. However, after synthesis the signal is optimized out since it's not driving anything (of course it will be driving...
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16 years ago
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Xilinx timming analysis
Hello, Somebody can explain me what is the "Tdcmino" signal in a DCM ? The "Tdcmino" delay is very high (more than 5 ns) and I don't what is it ! please Help. Laurent. have fun.
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16 years ago
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Gemac on ML402
Hi, Does anyone run the Gemac on a Xilinx ML402 board ? I try to use the example design that comes with the core but it didn't work yet. For example, this example design doesn't have the phy_reset...
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16 years ago
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Why use small resistor for Vcco voltage regulator
In Xilinx application notes XAPP457 ( resistors used to adjust output voltage is only 22.6 and 38.3, shown in Figure 1 in the pdf file. According to LT1763 data sheet( ),shown in Figure 2. Adjustable...
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16 years ago
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Loading the design from Compact Flash...
Hi everybody, It's been a while I'm struggling with ML310 board to have my design loaded from compact flash to the Virtex II-pro FPGA on the board. I'm generating file using iMPACT and program the...
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16 years ago
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Why does a 36 x 36 Multiplier in a Xilinx Spartan 3E require 9 multipliers?
I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in a Xilinx Spartan 3E. I've tried to poke down into the RTL schematic, but I'm unable to push down into the multiplier block. Could...
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16 years ago
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Low Pin Count (LPC) bus code available?
I'm working on a Low Pin Count (LPC) bus interface and would like to double check my design with an existing implementation. Does anyone have an existing design they could share? Verilog source would...
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16 years ago
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question about fsl and microblaze
hi i'm just working on a project where i need to create an fsl interface for my custom ip core. i used the "create and import" peripheral wizard from the edk. the wizard gives me the following options...
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16 years ago
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Xpower
Hi All, I am trying to see the power consumption of some design using XPower with ModelSim generated .vcd file I get this message : WARNING:Power:1087 - Can't change frequency of net clk to 100.00Mhz...
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16 years ago
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Design security for pre-Virtex2 parts ?
Hi all, Has anyone ever tried to improve the security for the old Xilinx FPGA devices, which doesn't have the 3-DES encryption? If so what's the feasible approach ? So far I have no clue TIA,
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16 years ago
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iru1209 regulator
Hello all, i have a design finished a few month ago, that is working fine on a xc2s200-pq208, but when i port it to a xc3s400-tq144, it ain't work most of the time (depends on the synthesis process)...
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16 years ago
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Xilinx BSCAN primitives proper use
Has anyone managed to get the xilinx BSCAN primitives (for interfacing with the USERx jtag registers/comands) working robustly? I've found a depressing lack of information as to what the actual pins...
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16 years ago
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FPGA in Telecommunications
Hello All, I am curious what are main applications of FPGA in Telecommunications? It's well known (well, at least for some smart chaps :) ) that DSPs (Digital Signal Processing Systems) can be...
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16 years ago
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Actel Fusion FPGA
Hello, I am working on Actel Fusion FPGA. I am having problems with the ADC in my design. Can someone please help me with this? Thanks alot! Cheers!
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16 years ago
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I need a SDRAM controller
Hi everybody! I did a controller to SRAM, so, I need controller a SDRAM, like it=B4s more difficult, (refresh). I=B4m looking for som code free in vhdl. I have seen one code with double port of xilinx...
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16 years ago
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