I'm implementing a 36 bit x 36 bit multiplier with a 72 bit output in a Xilinx Spartan 3E. I've tried to poke down into the RTL schematic, but I'm unable to push down into the multiplier block.
Could you please explain architecturally why this requires 9 multipliers?
Thanks, Dale
Just a guess, but I imagine the multipliers are signed 18x18, so you can't use all 18 bits when you try to extend them?
You can do a 35x35 multiplier with four DSP48s, but doing a 36x36 takes more because you can't use the 18th (sign) bit in the LSB DSP48s. See fig 1-21 of this doc:
-Kevin
Thanks for the comments. That was correct. Because it's a signed multiply in blocks of 18x18 it reduces the throughput of each input by one bit. I implemented a 35 x 35 multiplier and it only used 4 multipliers as I would expect.
Thanks again, Dale
You only need two adders to extend a 35x35 to 36x36. Maybe you cann use the final adders in the DSP slice for that.
Kolja Sulimma
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