Field-Programmable Gate Arrays

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Virtex5 not for SONET or SDH

Hey guys, Be careful when using Virtex5 for SONET. The RocketIO tile only has 1 PLL used for transmit and receive on bo...
3 comments posted 18yrs
posted by hemulliken
3 comments posted 18yrs posted by hemulliken

Partial Reconfiguration of Virtex-5: ISE and EAPR?

Hi all, Does anyone know whether Virtex-5 devices are supported by the Partial Reconfiguration design flow. I understan...
7 comments posted 18yrs
posted by kpapadim
7 comments posted 18yrs posted by kpapadim

Single Top FPGA Tips

Hi all, I thought I would share this report that I just wrote called "Single Top FPGA Tips". http://www.burched.com/Bur...
8 comments posted 18yrs
posted by tony
8 comments posted 18yrs posted by tony

Simple Memory Read problem, help appreciated

Hi I have a strange bug in my simulation and cant figure out the error. I have a simple ram that contains data that sho...
11 comments posted 18yrs
posted by Gerry
11 comments posted 18yrs posted by Gerry

Simulator error 607

Hi everyone, I'm running Webpack ISE 9.2i (just updated to 9.2.04i/J40) on Suse10.1. This is not the 'blessed' RedHat b...
1 comments posted 18yrs
posted by boven
1 comments posted 18yrs posted by boven

1-Wire and Dallas DS1WM in Spartan

Hi! I have implemented the Dallas/Maxim 1-Wire master DS1WM (version v1.100) in a Spartan3A. It works fine most of the...
2 comments posted 18yrs
posted by noreply.larthe
2 comments posted 18yrs posted by noreply.larthe

OPB timer Microblaze

Hello all. below is a part of my code for an OPB timer attached to a Microblaze with no inerrupts. the timer counts cor...
2 comments posted 18yrs
posted by lastval
2 comments posted 18yrs posted by lastval

Problems with GDB in EDK 9.2

I posted this on the Xilinx EDK forum without success so far. I recently upgraded to EDK 9.2.02i and built up the TestA...
2 comments posted 18yrs
posted by jcr_alr
2 comments posted 18yrs posted by jcr_alr

ML505 with Petalinux

Has anyone successfully ported Petalinux in Microblaze (ML505) and used the SATA AHCI driver? Is the AHCI driver from Pe...
2 comments posted 18yrs
posted by muthusnv
2 comments posted 18yrs posted by muthusnv

simulator options

Hello, I am looking for a basic simulator which can help me with testing functionalities of my VHDL and Verilog designs...
1 comments posted 18yrs
posted by FPGA.unknown
1 comments posted 18yrs posted by FPGA.unknown

Modelsim Warning

I am getting the following warning in Modelsim # ** Warning: Design size of 10053 statements or 1 leaf instances exceed...
5 comments posted 18yrs
posted by FPGA.unknown
5 comments posted 18yrs posted by FPGA.unknown

Sythesisable subset of VHDL

Hi I have done some VHDL implementations that were successfully running on an FPGA. However, I still feel unsecure abou...
2 comments posted 18yrs
posted by Gerry
2 comments posted 18yrs posted by Gerry

New leonardo spectrum version has license errors

Hey everyone, Just wonderting if anyone else has upgraded Leonardo Spectrum in a while. I went from a (very) old versio...
1 comments posted 18yrs
posted by robquigley
1 comments posted 18yrs posted by robquigley

GCLK overmapped

Hello, From searching, I see that others have had this same problem, but the solutions were vague and old (2002). I'm u...
1 comments posted 18yrs
posted by markmcmahon
1 comments posted 18yrs posted by markmcmahon

How to optimize my design area to fit?

Hi all, I am currently building a Digital Down Converter on Xilinx System Generator 9.1 platform which unfortunately ov...
6 comments posted 18yrs
posted by hilo_pupu
6 comments posted 18yrs posted by hilo_pupu