Field-Programmable Gate Arrays

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DDR SDRAM Configuration problem on XUPV2P

Hi! So, I'm using XUPV2P board (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,794&Prod=XUPV2P). And I'm...
0 comments posted 15yrs
posted by hrcrnjak
0 comments posted 15yrs posted by hrcrnjak

FPGA cards with memory bus interface

Good day everyone I am fairly new to FPGA based architectures, and I'm interested in applications that are very sensiti...
0 comments posted 15yrs
posted by ka.aly
0 comments posted 15yrs posted by ka.aly

fpga

Hello dear all, I have run into a problem regarding the FPGA. The FPGA output signal amplitude is 3.3, and to drive my...
2 comments posted 15yrs
posted by user
2 comments posted 15yrs posted by user

USB support for XUPV2P

Does any one know an add on card that can be used with XUPV2P?
1 comments posted 15yrs
posted by manusha1980
1 comments posted 15yrs posted by manusha1980

Why feedback clock in SDRAM controllers?

I see it in many SDRAM controllers, e.g. ftp://ftp.xilinx.com/pub/applications/xapp/xapp608.pdf, and nobody explains WH...
10 comments posted 15yrs
posted by inte..j
10 comments posted 15yrs posted by inte..j

Soft Processors and Licensing

Just a bit about the project I'm working on: Have an FPGA gathering and manipulating data, and we need a processor to r...
12 comments posted 15yrs
posted by ajpkane
12 comments posted 15yrs posted by ajpkane

boldport

In a bit of a self promotional move, though probably pretty relevant to this group, I'd like to mention http://www.bold...
2 comments posted 15yrs
posted by saardrimer
2 comments posted 15yrs posted by saardrimer

remove Xilinx webtalk

Hi, How do I remove webtalk in Xilinx 13.1, I do run all the tools from a script not from GUI? I did run a trail license...
8 comments posted 15yrs
posted by michael_laajanen
8 comments posted 15yrs posted by michael_laajanen

NULL POINTER DEREFERENCE

Hello all, I am a fresher in this industry..... I am working on systemverilog... I have created a model for analog to d...
1 comments posted 15yrs
posted by rittu16
1 comments posted 15yrs posted by rittu16

ise 10.1 (Linux) contraints problem

Hello, all, I'm using Xilinx Ise 10.1 on a Linux system, and ran into a crazy problem. I took a previous design and str...
10 comments posted 15yrs
posted by elson
10 comments posted 15yrs posted by elson

Logic Accessible Clock

The Logic Accessible Clocks are entailed for example in http://www.cisl.columbia.edu/courses/spring-2004/ee4340/restric...
1 comments posted 15yrs
posted by intellij
1 comments posted 15yrs posted by intellij

Re: Lattice Breakout Boards

> Or, you could wait for the MachXO2 breakout ;) > - and I see they now have this real, at $29. > > http://www.lattices...
0 comments posted 15yrs
posted by as
0 comments posted 15yrs posted by as

Re: about slices in xilinx

> > > > > > > > > hi all, > > > > i have a doubt regarding no.of slices in xlinx > > > > what are slices? > > > what ar...
2 comments posted 15yrs
posted by ccon67
2 comments posted 15yrs posted by ccon67

Win an Altera DE0-Nano (Cyclone IV Dev Kit)!

Hey guys! Terasic Technologies is holding a contest to WIN the newly released Altera DE0-Nano! Head over to http://www....
4 comments posted 15yrs
posted by ayhoung
4 comments posted 15yrs posted by ayhoung

help with a power pc processor based software

i have implemented a powerpc based embedded system in a xilinix vertex-2pro device and trying out an extremely simple p...
9 comments posted 15yrs
posted by manusha1980
9 comments posted 15yrs posted by manusha1980