2 years ago
I'm dealing with some fast state machines and gate-level-timing
simulation of some components has been very helpful.
Now using a Cyclone V I found that I can't do timing gate-level timing
simulation, quartus does not generate the SDF file, the *.sdo file.
Altera/Intel says this on the documentation regarding simulation:
"Gate-level timing simulation is supported only for the Arria II
GX/GZ,Cyclone IV, MAXII, MAX V, and Stratix IV device families.
Use Timing Analyzer static timing analysis rather than gate-level timing
I don't even know how to interpret the last sentence, how
does the Timing analyzer give me the same info / graphical view of the
timings of the critical signals and buses that I'm trying to view ?
Any help ?