enum and Vivado

You might try boiling your code down to a minimum example and posting it. You might also try posting this in the Verilog group. It should get more traction there.

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  Rick C. 

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I think we need to see some code, but to note that:

enum { x, y, z } foo;

is declaring a variable foo, while:

typedef enum { x, y, z } Foo;

is declaring a type.

If you do the former twice I'd expect conflicts because foo has been multiple-declared.

Theo

It might depend where you're putting the `include. Is it inside the module declaration?

Since you are using Systemverilog, I would suggest ditching the `include an d using packages instead. I don't know if it's true for C, but in Verilog, precompiler directives are oldschool kludges. You are using Systemverilog , so you can put enum declarations in packages, which is much cleaner.

In fact, I'm doing the latter. I want a typedef but get the multiply defined error if I include that header file in two files.

I'll work on writing up some simplified code that shows the problem. It seems so simple what I'm trying to do that this error suggests I'm staggeringly confused about how enums or typedefs work. Or maybe include files.

It's outside the module declaration. I hadn't thought about trying to put it inside the module declaration.

I haven't run across packages, no idea what they are. Mostly I'm just edging into SystemVerilog so I could get enums and typedefs. I thought they'd make my code a little cleaner than playing games with `define.

If you were putting the `include outside the module declaration and move it inside, I would think that would fix the problem. If it's outside it migh t apply to all modules compiled after that one.

enums are great, especially for FSM state names, and allow you to see the s tate name (instead of a number) in a waveform viewer. (There are kludge wa ys to do this in Verilog-2005, but they are awkward.) I would use Verilog-

2009 (Systemverilog) constructs always, but I'm usually required to stick t o 2005 or earlier so as to be compatible with ASIC tools that are expensive but have parsers from the stone age. So I rarely use packages, but I wou ld if I could. It's a similar idea to `include, but more sophisticated tha n a cut-and-paste. You are definitely right to avoid `defines, though. Mo st `defines can be replaced by parameters, but enums are better than parame ters in some cases.

And that's the weird difference between C and Verilog that was baffling me. In C, definitions like that only apply to the file, not once it's defined it applies to all follow-on files too. Very strange.

Moving the `include inside the module definition kind of worked. I mean it did, but it prevents me from then using the enum or typedef in the ports coming into and out of that module. I can work around that.

I'd love to use packages as they look like they do much more of the right thing. And I tried it with Vivado and it worked just fine. While I'm not using ASIC tools, I am also using Icarus Verilog for fast turn-around testing and it only understands bits and pieces of SystemVerilog. It can parse (and ignore?) the package declaration but it can't handle the import statement. Sigh.

Anyway, you've put me on the right track. Thanks a lot.