Passing digitized data to design

Hello,
Is there a resource that can help me understand how to pass digitized data
(from a waveform) to a design that I have for verification? I'm getting int
o FPGA development and have created a simple filter. I wanted to test it ou
t on audio data that I can generate and see that the filter actually works,
but I haven't found a way to actually "pass" data to a design.
Thanks
Mohammed
Reply to
Mohammed Billoo
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a (from a waveform) to a design that I have for verification? I'm getting i nto FPGA development and have created a simple filter. I wanted to test it out on audio data that I can generate and see that the filter actually work s, but I haven't found a way to actually "pass" data to a design.
Do you mean a "design" in a simulation or in an FPGA? In an FPGA I would e xpect your system to already be capable of sending data to it. If not, how do you plan to use the design?
In a simulation you need to have the data in a file which can be read out b y a test bench and provided to the simulated FPGA by simulating the interfa ces to the FPGA.
I typically spend as much effort on the test benches for my designs as I do the designs themselves.
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  Rick C. 

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Rick C
Sorry, yes I meant in simulation. I imagine there are many good resources o nline that show how to set up a testbench for this purpose in Vivado.
Thanks
ata (from a waveform) to a design that I have for verification? I'm getting into FPGA development and have created a simple filter. I wanted to test i t out on audio data that I can generate and see that the filter actually wo rks, but I haven't found a way to actually "pass" data to a design.
expect your system to already be capable of sending data to it. If not, h ow do you plan to use the design?
by a test bench and provided to the simulated FPGA by simulating the inter faces to the FPGA.
do the designs themselves.
Reply to
Mohammed Billoo
I assume Vivado is a simulation tool? That is agnostic to the issue. You simply need to learn how to use the HDL you are using. Once you know that you can write the test bench to operate the other side of the interface from the FPGA.
What sort of interfaces do you have?
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  Rick C. 

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Rick C
It looks like there is non-synthesizable VHDL that will allow me to read in a file, convert from unsigned to a std logic vector and pass it to my module as a DUT.
Reply to
Mohammed Billoo
rces online that show how to set up a testbench for this purpose in Vivado.
You simply need to learn how to use the HDL you are using. Once you know t hat you can write the test bench to operate the other side of the interface from the FPGA.
in a file, convert from unsigned to a std logic vector and pass it to my mo dule as a DUT.
Not sure what you mean by "there is", but yes, your test bench does not nee d to be synthesized since it is not going to be part of the design compiled for your FPGA. It will be up to you to write it and make it work like the environment your FPGA will work in.
There were times I even simulated analog hardware like an RC filter to proc ess the output of a single bit DAC and produce an "analog" output. The sim ulator allows plotting the value of an integer as a waveform reproducing my output signal like an oscilloscope. The test bench could sample that anal og signal, create a sound file which could then be played back outside the simulation.
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  Rick C. 

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Rick C

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