FIR choice

Hi all, I'm implementing a Digital Down Converter for Virtex II pro device.

I think I'll not use the builtin DDC IP core because I'm using this project to learn something about FPGAs and VHDL.

Essentially I have samples coming from an A/D at 64MHz. The signal is bandpass, centered at 112 MHz and it can have to different bandwidth

5MHz and 25MHz.

I've already implemented in VHDL the I and Q components splitting, now I have to filter these signals with low pass filter and decimate the sequence. I'm going to use the "MAC FIR Filter" IP core (shipped with Xilinx ISE).

I have some questions, I'm a newbie digital designer so please consider this :-)

1) using a polyphase decimator is exactly the same of using a single rate filter and then downsampling the output?

2) I need the same filter on both I and Q channels, so I think I could set the core to use 2 channels, but I'm not sure how it works, is it realized with time sharing? I'd need the two samples I(k) Q(k) at the same time.

Thank you all, and

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Nemesis
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The CIC core is often used after a DDC. It gives large decimations at low cost but does usually require a cleanup FIR filter following the CIC.

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pedro uno

Mentre io pensavo ad una intro simpatica "pedro uno" scriveva:

Yes, I read this, but I don't need a large downsampling. Probably I'll need a 10 factor for the 5MHz signal. But I still have doubts on the two topics I wrote in the previous article.

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Nemesis

now I

consider

could

Reply to
mediatronix

I missed your original post, so I'll reply here.

1) the polyphase decimator is a mathematical manipulation to reduce the computational load. From a black box perspective, it provides the same output as you would have using a single rate filter followed by a decimator (dropping output samples). The difference is if you are clever about your filter implementation, you don't have to do all the computation for samples that are dropped. The polyphase filter takes advantage of that fact. It consists of R sub-filters whose outputs are summed. Each subfilter is running at the decimated sample rate instead of the input sample rate, so you get a reduction of the computations per unit time by a factor of R (R is the decimation ratio).

2) Multichannel operation is achieved by doubling the tap delays and interleaving the samples from each channel. The physical filter is operated at C times the sample rate (C is the number of channels). In order to do that, you need a multiplied clock and your logic has to be fast enough to operate at the increased clock rate. The reason for doing this is to reduce the size of the hardware by time-sharing (the classic time-area trade-off).

Where you have multiple bandwidths, you've got an opportunity to change the output sample rate to match the selected bandwidth. The advantage to using a CIC filter is that the filter shape referred to the output sample rate is nearly independent* of the decimation ratio. That means that you can follow the CIC with a filter that does not have to be changed when you change the bandwidth. In your case, you have only two bandwitdh settings, so it is not unreasonable to change filter coefficients to change the bandwidth. In either case, if you have a sample decimation ratio greater than 2, it is usually more efficient in terms of computation and amount of hardware to use a multi-rate approach where you decimate in each stage of a multi-stage filter. My DDC designs typically include a mixer followed by a CIC filter, followed by two stages of decimate by 2 FIR filters, the first of which is a halfband filter with a relatively small number of taps (typically around

15). If using a CIC, you'll want the final bandwidth to be no more than 1/4 the CIC's first null in order to keep the CIC's droop manageable.

  • The CIC filter response has a very small component that is dependent on the ratio, which is only minimally noticible at ratios less than about 15.

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--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
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Reply to
Ray Andraka

Mentre io pensavo ad una intro simpatica "mediatronix" scriveva:

Thanks! this tools are great, I'm enjoying very much the filter designer.

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Reply to
Nemesis

Mentre io pensavo ad una intro simpatica "Ray Andraka" scriveva:

[...] Thanks, now it's clear.

Ok, I have some problems with clocks. What is the System Clock referenced in the IP core creation GUI? How it is related to the samples clock (the clock I use for the A/D)? It seems that this system clock has to be greater (or equal) than the sample clock. I have to send to different clock signals to the chip?

Thanks for the answers, I also visited your web-site and I found in it some interesting papers.

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Nemesis

The system clock is usually some integer multiple of the sample (A/D) clock. In order to minimize the hardware, you'll want to run the clock as fast as your design will allow so that you can take advantage of multiple clocks per sample. You usually can use the clock managers in the FPGA to obtain the multiplied clock. For multiple channels in a single filter, your clock should be an integer multiple of (channels*sample clock).

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759
Reply to
Ray Andraka

Mentre io pensavo ad una intro simpatica "Ray Andraka" scriveva:

OK, so I don't have to provide this system clock on a pin, I have only to provide the sample clock?

I apologize for the dumb questions but I'm a newbie in digital design.

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A fool and his money are soon partying.
 
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Reply to
Nemesis

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