Field-Programmable Gate Arrays

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Xilinx - ucf file parsing errors

The Xilinx memory generator tool generates ucf files that have lines in them such as: NET "ddr1_top0/data_read0/fifo*_w...
1 comments posted 21yrs
posted by sbakke
1 comments posted 21yrs posted by sbakke

1394 Dcam wiht Xilinx FPGA

First of all I do not have any experiance with FPGA's because my background is software programming. I wonder if anyone...
0 comments posted 21yrs
posted by schwn
0 comments posted 21yrs posted by schwn

C Manual for Microblaze Software

I should develop a program for my embedded system based on microblaze. Where I can find a good manual with also Xilinx t...
1 comments posted 21yrs
posted by marcotoschi
1 comments posted 21yrs posted by marcotoschi

FIFO i Handel-C

Szukam sposobu implementacji kolejki fifo o dlugosci 512 bajtów .... jak sie do tego zabrac??
0 comments posted 21yrs
posted by marko
0 comments posted 21yrs posted by marko

Spartan 3 to tempsensor interface

Hi, I'm thinkin go of designing a heating/cooling system with VHDL an need to interface my Spartan 3 board to a real tem...
13 comments posted 21yrs
posted by rgebru
13 comments posted 21yrs posted by rgebru

About the usb access in board ML310!

Hello I am doing my thesis on Xilinx ML310 board. My target is t realise the real-time image processing. First I have t...
3 comments posted 21yrs
posted by fengmingxin_714
3 comments posted 21yrs posted by fengmingxin_714

Stapl, Xilinx, Altera Jam, XCF02S and iMPACT

Hi, I was wondering if anyone has tried to use a stapl file generated from Xilinx iMPACT software to program a XCF02S u...
0 comments posted 21yrs
posted by dscolson
0 comments posted 21yrs posted by dscolson

ISE 7.1 WebPack + EDK 6.3

Hi, Im a poor student who purchased the 6.3 version of the EDK a few months back. Uptill now I have been using the eval...
5 comments posted 21yrs
posted by pbs
5 comments posted 21yrs posted by pbs

Bit-Rounding Algorithm

Hi All, If anyone knows of a bit rounding algorithm, please forward the information to me. I am trying to round-off 24...
4 comments posted 21yrs
posted by saurster
4 comments posted 21yrs posted by saurster

Newbie: Slow FPGAs

I am probably opening a can of worms, but why are FPGAs so slow? The CPU cores at www.opencore.org represent an ever gr...
21 comments posted 21yrs
posted by dave
21 comments posted 21yrs posted by dave

Beginning Xilinx FPGA Tutorials?

Where to find Tutorials for using Xilinx FPGA? How to learn about Xilinx FPGAs, use ISE 6.3i and EDK 6.3i tools? Folks,...
4 comments posted 21yrs
posted by oth3ll0
4 comments posted 21yrs posted by oth3ll0

Xilinx System Generator, Gateways not implemented

Hello, I have problems with gateways in System generator 6.1.1, ISE 6.103, Matlab 6.5.1. I use a XtremeDSP Development...
3 comments posted 21yrs
posted by salomon
3 comments posted 21yrs posted by salomon