Latest threads in Field-Programmable Gate Arrays

divide by 2^n, n=21..37 ==> 3 Virtex Slices !!

Hi below is possible the most dense divide by 2^n ever implemented on any FPGA: divide by 2^37 takes only 3 Virtex Slic...

8 21yrs

antti

8 21yrs antti

Xilinx backups

What is the best backup procedure for Xilinx? I have used snapshot which seems to copy the whole directory into the cur...

4 21yrs

bradsmallridge

4 21yrs bradsmallridge

OPB component for serial Flash?

Hi! I want to store the program code for the Microblaze processor in my serial configuration Flash and use a bootloader...

2 21yrs

alles

2 21yrs alles

TI SN54LVT8980A JTAG TAP MASTER

I am currently trying to use the SN54LVT8980A JTAG TAP MASTER controller to program FPGA PROMS. I have put the chip on...

0 21yrs

heynow567

0 21yrs heynow567

Difference between simulation types

Hi everyone, can anybody tell me the real difference between - behavior (guess this is pure VHDL) - post-translate (gue...

3 21yrs

64bitNOnoNOSPAM

3 21yrs 64bitNOnoNOSPAM

Importing waveforms from ASCII files

Hi all, I'm trying to test a filter I implemented with Xilinx ISE 6.1, so I created a testbench waveform. I'd like to i...

2 21yrs

nemesis

2 21yrs nemesis

clock division using DCM, how?

Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine ex...

3 21yrs

tkanmijnischelen

3 21yrs tkanmijnischelen

ML300 Gigabit Ethernet Issues...

I'm trying to get a gigabit ethernet design to work with Xilinx's Gige MAC (gemac 5.0/pcs combination) through the rock...

1 21yrs

nweaver

1 21yrs nweaver

Lattic ECP/EC -- Partial Run-time Reconfiguration??

Hi, Anybody can tell me if Lattic ECP/EC FPGA devices support partial run-time reconfiguration? If yes, is there any rel...

1 21yrs

nickelyg

1 21yrs nickelyg

NIOS II power-on reset

Dear everybody, I have a problem on some production boards based on the Altera Cyclone FPGA. The boards have installed...

2 21yrs

alessandro.strazzero

2 21yrs alessandro.strazzero

Problem writing Pinouts on Webpack

I bought a Digilent Inc S3 Board, and now I'm starting to use it. The first thing I'm trying to do is implement a count...

4 21yrs

jorchi

4 21yrs jorchi

VREF for SSTL out only / PCB

Hallo, in a hobby-design with Spartan3-200-TQ144 I wish to use DDR-RAM (Samsung SSTL2-25, max. 400MBit/s per IO, 32 Bit...

3 21yrs

post

3 21yrs post

LogicAnalyzer ispTracy

Hi, I am trying to implement a debug template in an EC-FPGA (LFEC20E) with the Lattice ispTRACY IP Manager. I am facing...

1 21yrs

nospam_nussspucke

1 21yrs nospam_nussspucke

SystemC and OCP-IP

Hi, I'd like to learn how OCP-IP works. Does anyone have a link showing a step-by-step example describing an IP with Sys...

0 21yrs

koudri

0 21yrs koudri

changing DDR2 pin LOC on UCF generated by MIG for virtex4

Am I allowed to change the pin location on the same bank generated b MIG for my virtex4 design ? Would it not be a hass...

2 21yrs

lamgh

2 21yrs lamgh

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