I have a problem on some production boards based on the Altera Cyclone FPGA. The boards have installed NIOS II CPU. The problem regards the power-on sequence because some boards are not able to power-up correctly (seems NIOS II CPU doesn't execute first operative code).
The development was made on a C7 speed grade FPGA and I didn't experience such problem. The boards where the problems were detected have installed the C8 speed grade Cyclone.
The power-on and reset circuitry comes from Altera's Cyclone development board. I think the problem is around the FPGA speed grade, but I was not able to find the reason. My system works at 64 MHz which is a well supported frequency by the C8 speed grade device.
Did you experience my same problem ? Any tips to workaround the problem will be appreciated