Problem writing Pinouts on Webpack

I bought a Digilent Inc S3 Board, and now I'm starting to use it. The first thing I'm trying to do is implement a counter and test my Hex 2 SevSeg controller. I have put the correct FPGA en my Webpack project and have read Digilent's reference manual, but when I try to write the pinouts that digilent states, the Webpack does not accept them and clears the box automatically(E13,G13,N15,P15,R16,F13,N16).

Any ideas why this could be?



----------- al912912

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You did not say which version of ISE you were using but I have had it working for version 4.2, 5.1 & 6.3.

I have a few things for you to check: (1) Have you created an Implementation constraints file (.UCF) and is it associated with the top level of your design? It should appear as a "U" module immediately below (and indented) your top levels "V" entry in the "Sources in Project" list. If not add new source of type "implementation constraints file".......

(2) Uses the Edit Constraints(text) option in the processes list (in the "User Constraints section) you should see some lines like...

NET "ssg" LOC = "E14" ; NET "ssg" LOC = "G13" ; NET "ssg" LOC = "N15" ; NET "ssg" LOC = "P15" ; NET "ssg" LOC = "R16" ; NET "ssg" LOC = "F13" ; NET "ssg" LOC = "N16" ; NET "ssg" LOC = "P16" ;

where "ssg" is the name of the signal in your top level entity declaration. You can put the lines in the UCF manually, the definitions are in the examples on Digilent's web site.

Hope this helps,


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Tim Good

Yes, I had done everything. the ucf was created Ok. Usually the pinouts I had written all started with a P, now the digilent reference talks about pins not starting with a P. Those are the ones not working.

If I write the lines directly to the UCF file then they do not map.

" - LOC constraint G13 on SEV_SEG is invalid: No such site on the device. To bypass this error set the environment variable"

And that's for each one taht doesn't start with a P.

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I found the error, although I had the correct device, I didn't had teh correct package.



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Hi there,

We developed DesignF/X to help prevent/solve these kinds of issues amongst many others by helping create highly accurate pin assignment (.UCF output) for Xilinx devices. Explicit device/package matching is included as is clock/data pin correlation, etc. (Sorry, no Altera support for a while). S3, VII and VII-P are well supported.

You can download a free trial from

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- system requirements and additional information listed there. Download should take a few minutes at the most.

With best wishes, Manu

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