can anybody tell me the real difference between - behavior (guess this is pure VHDL) - post-translate (guess this is after synthethis) - post-map - post place and route (guess this is when the design is "final" and is known where to be put in the FPGA)
This is purely behavioral - it literally just simulates what the VHDL describes, without any device-specific timing or anything.
Post place-and-route simulates the behavior with timing, after the design has been fitted into the device. I assume that post-map and post-translate just have less, or less accurate, information (I don't do these type of simulations).
As an example:
foo: process(clk) begin if rising_edge(clk) then if rst = '1' then dout
Post-map also takes care of some delays - but which ones. I can't use the post place and route, cause I can't count on this, when I don't simulate the whole design since the routing will not be correct?
I'd make the assumption that it would probably just take the delays from the actual logic into account, without routing delay - for instance, the combinatorial delays through X many luts.
Post place-and-route is probably worth it still, as it will give you some idea of routing delays - the only accurate simulation is that of the final product though.
Basically, there is no guarantee of how the design will be finally routed - you might change something, and the design will then be routed differently. There are ways to mitigate this, if it's really necessary (RPMs, directed routing etc). What are you trying to do? (Do you actually need a full simulation with all the extra timing information?)