I get this message when i synthesize my code "you may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on xilinx devices, or with a specific template that is not supported"
I have this signal sram_data which is of type array(0 to 255) of std_logic_Vector(7 downto 0). I am assigning values to each element sram_data(N) inside a state machine and this message pops up when i synthesize. any comments on how i can fix this?
thanks
Try instantiating a block ram. You can then initialize the contents either in your .ucf file or in your VHDL source. For example of initialization syntax, refer to the lib.pdf available in installation directory of xilinx ie /xilinx/doc/usenglish/docs/lib/lib.pdf
-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc.
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Remember that a Xilinx BlockRAM is clocked. Even to read, you must supply a clock. In that respect these BlockRAMs are different from "conventional" RAMs, where the reading is combinatorial. Peter Alfke
Good chance you are not using it as a synchronous RAM. Look at the synthesis templates either in your synthesizer or on Xilinx's synthesis guide. It would be helpful if you posted the code in question so that we can see what you are doing.
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
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