using (verilog) reg as memory

Most synthesizers will infer such a block as FPGA block memory if the HDL is written in a certain way. Look at the user's guide of your synthesizer for more details.

-Kevin

There are two ways to synthesize a memory in an FPGA. One is to use verilog's reg as you suggested, the other one is to use Vendor Specific Primitive. Using verilog's reg is the most portable one. It works with all FPGAs with little or no modification. But it takes valuable space in your FPGA logic that otherwise can be used for other purposes. An alternative way is to instantiate Vendor Specific Primitive. This method is not portable. You must instantiate different primitive for different chips family and vendors. However, you will safe a lot of space in your chips since instantiating a Vendor Specific Primitive means you will use a dedicated memory in the chip, leaving the logic free to be used for other purposes.

Hendra

Most of the synthesis tools are able to infer dedicated RAM blocks.

Jim snipped-for-privacy@yahoo.com (remove capital letters)

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With XST, how do I know that my code is synthesized to a RAM made from the logic, or RAM made from the dedicated RAM blocks?

Hendra

The synthesis report will tell you if the tool inferred RAM.

Jim snipped-for-privacy@yahoo.com (remove capital letters)