Field-Programmable Gate Arrays

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Mixing synchronous and asynchronous reset

Is there any hazard to mix synchronous and asynchronous reset? I am making an RS232 controller and I generally use asyn...
3 comments posted 21yrs
posted by kclo4_NO_SPAM_
3 comments posted 21yrs posted by kclo4_NO_SPAM_

using FPGA JTAG pins as general purpose I/O

Hi I assume this not so widely known and most likely has not so much actual use, but in some cases it may be useful to...
0 comments posted 21yrs
posted by antti
0 comments posted 21yrs posted by antti

Multi-FPGA PCB data aggregation?

Hello! I'm trying to build a 20-FPGA (spartan-3s, XC3S400-TQ144s) board for a class project to investigate the use of F...
19 comments posted 21yrs
posted by acetylcholinerd
19 comments posted 21yrs posted by acetylcholinerd

Bus expansion

Hello, how do I extend buses in Quartus Schematic Editor? Say, for instance, there is an input "phase_offset[23..0]" an...
1 comments posted 21yrs
posted by wyderskiREMOVE
1 comments posted 21yrs posted by wyderskiREMOVE

some +. for Altera

Hi first - I am a very Xilinx biased (possible because I have way more Xilinx boards) but the latest Quartus seems real...
12 comments posted 21yrs
posted by antti
12 comments posted 21yrs posted by antti

Initializing Altera MEGARAMs in simulation

For whatever reason, I need to be able to initialize the M-RAMs in Altera chips, and I need to do this in a timing simu...
6 comments posted 21yrs
posted by nospam
6 comments posted 21yrs posted by nospam

cheap Xilinx tricks

Hi, Given a Spartan 3 chip, what I'd like to do is arrange two pins as an LVDS receiver *and* simultaneously have a reg...
11 comments posted 21yrs
posted by jjSNIPlarkin
11 comments posted 21yrs posted by jjSNIPlarkin

iMPACT Boundary-Scan Error

Hi, a few months ago I purchased a Spartan-3 Starter Kit from Xilinx. It had been working fine up until recently. I nev...
2 comments posted 21yrs
posted by daragoth
2 comments posted 21yrs posted by daragoth

Middleware for FPGA-based computing

Koan Corporation has released the first version of the Reconfigurable Computing Management System, RCMS. It integrates...
0 comments posted 21yrs
posted by tyler.reed
0 comments posted 21yrs posted by tyler.reed

xilinx+modelsim total newbie

Hi, I have downloaded Xilinx ISE 7.1 webpack and Modelsim 6 free edition. I need Xilinx for my digital circuits course....
1 comments posted 21yrs
posted by hacka
1 comments posted 21yrs posted by hacka

Onchip SRAM Vs Registers

Hi all, Can anyone tell me what is the threshold point(memory size) to opt for Onchip SRAM instead of FlipFlops , consi...
1 comments posted 21yrs
posted by john.deepu
1 comments posted 21yrs posted by john.deepu

About the ethernet access on the ML310 board!

Hello I want to access the ethernet on the ML310 board to transfer dat to a PC and receive data from a PC. But I find t...
0 comments posted 21yrs
posted by fengmingxin_714
0 comments posted 21yrs posted by fengmingxin_714

About the socket in ML310

Hello I want to set up a conncetion between ML310 and the PC. I set th PC as server and the ML310 board as a client. Is...
0 comments posted 21yrs
posted by fengmingxin_714
0 comments posted 21yrs posted by fengmingxin_714

nios-convert

Nios-convert is causing me grief. I am converting a 2249kB srec to a .mif but getting the following error message: nios...
0 comments posted 21yrs
posted by evan1979
0 comments posted 21yrs posted by evan1979