Hi,
I'm picking up FPGA/CPLD design after a brief introduction in school a long time ago. My tool setup is the utilities supplied by Xilinx ISE
7.1 on Linux, with Icarus Verilog and gtkwave for pre and post synthesis simulation. Am I correct in thinking that Xilinx left some of the built in simulation capability out of the Linux version of their Webpack?Anyone else out there in the same boat? Are there any good FAQs out there to get me quickly started using this sort of chain? Are there any classes or seminars based around a Xilinx+Icarus combination, especially in the Portland, OR area?
regards,
Alex Alex at dee en el en kay dot com