Hello. I am writing VHDL code to be synthesized on a Xilinx Spartan II FPGA. For the past month, I've been beating my head against one problem with synthesizing the latest version of my code. I am using the Xilinx Webpack IDE V7.1.01i available for free from . Synthesis usually takes about a minute with my previous code versions. When I added a few lines about a buffer and references to that buffer, and try to synthesize, the synthesis goes to 66% of completion normally, but then stays there for about 15 minutes before spitting out an out of memory error:
ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 1954536 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. ERROR: XST failed Process "Synthesize" did not complete.
I have stripped my program down to the simplest version that still exhibits the problem:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity frameCapture is port ( clk :in std_logic; lineBuffer : out std_logic_vector(1780 downto 0); --will buffer most significant 5 bits of each pixel on even lines. UV: in std_logic_vector(7 downto 0)); --Digital output from camera. UV bus. end frameCapture;
architecture reg_transfer of frameCapture is
signal bufPosOne, bufPosTwo, bufPosThree : integer range 0 to 1785; --are five more than they needs to be to prevent negative numbers. signal colCount : integer range 5 to 25 :=5; -- I picked these values in this example so that bufPosTwo and bufPosOne are obviously -- between 0 and 1785. begin