How to map FPGA pin outputs and use User Constraints File (UCF) ?

Some of the xilinx fpga pins are wired to leds. P39 for instance is wired in such a way. In my design I have a vhdl counter and want to direct ISE (v.6.3i) to tie the output of the counter to P39. What is the way to do this?

It seems that PACE does this, but then Floorplanner and FPGA Editor seem to do something similar to this as well. When I tried to use PACE, I saw I could specify the Loc as "BANK6", but could not figure out how to directly assign to the pin #. In Floorplanner I could select File->Read Constraints..., but wasn't sure this would do what I wanted either.

In Xilinx ECS I could create a schematic that wires together the vhdl counter. It occurs to me that this is also a possible place to assign the output to P39. Is that true?



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IMO, the easiest to do this is in a UCF file. If you like PACE, it will create one for you. Otherwise, take an existing (non trivial) ucf, and modify it. Beware of busses notation, between , (), and [] ! Make sure your ucf text file is in your projnav, attached to your top level entity. And make sure you dont ask for the option to "ignore" it !!!

Bert wrote:

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Hi, I had the same problem too. PACE: Click on the package view tab at the bottom of the screen. This will show you all the BGA package pins and their functions ( I/O, clock, Gnd etc) on a nice graphic. Next drag the module port name from the left of the screen to an appropriate pin on the package pin diagram and drop it.

Then just save and exit. The UCF file will show up on your projNav.


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