Latest threads in Field-Programmable Gate Arrays

Last rites declaration of Ioannes Paulus PP. II (Karol Wojtyla)

"The unforgiveable sins this earth must confront and overcome are Nationalism, capitalism, and hoarding. The idea of ev...

0 21yrs

john_paul_ii

0 21yrs john_paul_ii

how to use both FFs in a CLB's slice using LOC or RLOC

While using RLOC (under ISE6.3i) I can assign a single FDC primitive to a specific slice in a CLB but cannot assign bot...

8 21yrs

aee

8 21yrs aee

XC95108 problem

Hi, I'm using the XC95108 CPLD and Xilinx ISE 7.1.01i. The problem I am having is that outputs are inverted when they a...

4 21yrs

rossm

4 21yrs rossm

PLX-9656 Controller interface

has anyone come across a PCI FPGA design using PLX-9656 Controller and Xilinx FPGA. We are using the MPRACE board and n...

1 21yrs

wallge

1 21yrs wallge

Xbox , chip mod & CPLD

Hi, Does anyone have already heard about the CPLD that are part of chip mod for console?? And if there is any website ta...

2 21yrs

kclo4_NO_SPAM_

2 21yrs kclo4_NO_SPAM_

XMD : Running XMD with Caches on

Hello, I would like to know whether turning on the caches in the PPC influences the functionality of XMD. 1) For instan...

1 21yrs

njoroge

1 21yrs njoroge

EDK:Question regarding opb_uart

Hi, Does anybody know where can I find datasheet of UARTlite IP core with detailed information of the signals and its wo...

2 21yrs

ranjeeta.patil

2 21yrs ranjeeta.patil

USB blaster

Hello: I have seen a couple of Altera development kits that allow you to program the FPGA using a USB port (instead of...

1 21yrs

sellthispiggy

1 21yrs sellthispiggy

Open PowerPC Core?

Does such an animal exist? I have looked around but as of yet Ive not seen one. Saw reference to a couple of non-open o...

20 21yrs

Ziggy

20 21yrs Ziggy

IPIF Signals

How do you connect custom IP cores to Microblaze using IPIF? Should all interface signals for the IPIF be on the top le...

2 21yrs

milind.parelkar

2 21yrs milind.parelkar

RAMB16_S9

Hi, I am trying to use RAMB16_S9 to store some data. Since this is my first time doing this, I am trying to test it to...

13 21yrs

ann.lai

13 21yrs ann.lai

Question regarding EDK

While creating a new design using EDK, in ADD/EDIT CORES -> PORTS tab Signals can be separated into external ports and...

4 21yrs

milind.parelkar

4 21yrs milind.parelkar

[info] Sine generation

Hello, my experiment has shown that high-quality sine wave can be easily generated using linear interpolation. A simple...

4 21yrs

wyderskiREMOVE

4 21yrs wyderskiREMOVE

ModelSim XE and WindowsXP

Hi all, I'm trying to install ModelSim XE (both II and III) on a WindowsXP box but I can't get it working when I login...

8 21yrs

nemesis

8 21yrs nemesis

OPB Master

Hi everyone , Can any one in brief tell me how to design a Master - Slave IP Core on the OPB - Bus ..I just need a desi...

1 21yrs

beeraka

1 21yrs beeraka

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