While using RLOC (under ISE6.3i) I can assign a single FDC primitive to a specific slice in a CLB but cannot assign both flip-flops in a slice. RLOC parameter is just RxCy.S0 or RxCy.S1 but each slice has two flip-flops and I see no way to use both. Have not found any primitive or attribute to do thi assignment. It is the same when using XORCY and the design endup wasting half of the resources (for this particular segment of the design).
So, is there a way to instruct the tool, in the VHDL (XST) source, to use resources in this such detailed way?
The second question to follow is: is there a way to instruct the tool (map/router) to use, say, long lines instead of lots of local lines when sourcing several CLB inputs with a single signal? It also seems that there is a kind of check-list for router and when changing the direction/shape of a RLOCed circuit it uses different resources to make the connections. I cannot find a document in Xilinx web site instructing how to better use the tools according the device's architecture, tool's processing schemes and design goals.