Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

ISERDES2 divide factor

Hi all, I have a Spartan-6 LX45 board with a whole bunch of lvds going in and out at a rate of 780mbps. After running o...
3 comments posted 14yrs
posted by jonpry
3 comments posted 14yrs posted by jonpry

EDK problems

Does anyone have experience of using the Altera and Xilinx embedded software? I have been using EDK but I am getting ve...
2 comments posted 14yrs
posted by maxascent
2 comments posted 14yrs posted by maxascent

Read output from external chip using microblaze

Hi all I got stuck with my design. I'm planning to use microblaze in ML505 board to read my full custom chip output and...
4 comments posted 14yrs
posted by nana_7488
4 comments posted 14yrs posted by nana_7488

Logic Glitches in Spartan-3?

I've got a 24-input AND gate that I'd like to avoid having add another register delay to before I toss it across a clock...
16 comments posted 14yrs
posted by rgaddi
16 comments posted 14yrs posted by rgaddi

Announcement: Sigasi integrates with Aldec compiler

Dear hardware designers, In its latest release, Sigasi Pro 2.4 integrates with the Aldec Riviera-PRO simulator to accel...
0 comments posted 14yrs
posted by philippe.faes
0 comments posted 14yrs posted by philippe.faes

ITU656 to Mpeg4 with Fpga?

An ADV7181BBSTZ - PAL/NTSC Video Decoder coverts an analogue video camera signal to ITU656 and YCrCb 4:2:2 [http://en.w...
2 comments posted 14yrs
posted by stephanusr
2 comments posted 14yrs posted by stephanusr

Xilinx ISE Multiple Drivers Error

Hi folks, I seem to have convinced ISE to output incorrect multiple-driver error messages. I've reduced the example to...
15 comments posted 14yrs
posted by chead
15 comments posted 14yrs posted by chead

banks and its association with options

oops, After discussing about the banks, it is certainly appropriate to take into account the monitoring of the options w...
0 comments posted 14yrs
posted by <Steve
0 comments posted 14yrs posted by <Steve

Spartan-6 66mhz pci

I'm trying to make a simple PCI interface in a XC6SLX45. In the end I'll probably go with the premade Xilinx core but I...
3 comments posted 14yrs
posted by jonpry
3 comments posted 14yrs posted by jonpry

Synthesis Problem

I have this code written in verilog for a counter but my program xilinx ise 14.1 finds 2 errors: ERROR:Xst:899 - "numar...
8 comments posted 14yrs
posted by andreiopariuc
8 comments posted 14yrs posted by andreiopariuc

FDE vs latch?

What's the big deal about a latch? Is it less efficient in floorspace than an FDE? Or is it just some amount of combinat...
6 comments posted 14yrs
posted by boat042-nospam
6 comments posted 14yrs posted by boat042-nospam

Interfacing a circuit in an FPGA to a PC

If you have an interest in exchanging data between circuitry in an FPGA and= a PC, I have written a simple GUI that dem...
2 comments posted 14yrs
posted by j.b.w.webber
2 comments posted 14yrs posted by j.b.w.webber