Latest threads in Field-Programmable Gate Arrays

Questions about LCMXO2280-B-EVN and LCMXO2-1200ZE-B-EVN ev kits

There are too many FPGAa and CPLDs. I can see that LCMXO2280-B-EVN has 8 40-pin connectors, which is important to me. B...

5 14yrs

sala.nimi

5 14yrs sala.nimi

PRNG

I need a multi-bit PRNG which generates a sequence of 10-bit pseudo random numbers. Can I use a LFSR of sufficient leng...

18 14yrs

theller

18 14yrs theller

Variables, signals: behavioral and post-route simulation

I'm learning the diff between variables and signals, and I've found this site: http://esd.cs.ucr.edu/labs/tutorial/sig_...

3 14yrs

aleksazr

3 14yrs aleksazr

ISERDES2 divide factor

Hi all, I have a Spartan-6 LX45 board with a whole bunch of lvds going in and out at a rate of 780mbps. After running o...

3 14yrs

jonpry

3 14yrs jonpry

EDK problems

Does anyone have experience of using the Altera and Xilinx embedded software? I have been using EDK but I am getting ve...

2 14yrs

maxascent

2 14yrs maxascent

Read output from external chip using microblaze

Hi all I got stuck with my design. I'm planning to use microblaze in ML505 board to read my full custom chip output and...

4 14yrs

nana_7488

4 14yrs nana_7488

Logic Glitches in Spartan-3?

I've got a 24-input AND gate that I'd like to avoid having add another register delay to before I toss it across a clock...

16 14yrs

rgaddi

16 14yrs rgaddi

Announcement: Sigasi integrates with Aldec compiler

Dear hardware designers, In its latest release, Sigasi Pro 2.4 integrates with the Aldec Riviera-PRO simulator to accel...

0 14yrs

philippe.faes

0 14yrs philippe.faes

ITU656 to Mpeg4 with Fpga?

An ADV7181BBSTZ - PAL/NTSC Video Decoder coverts an analogue video camera signal to ITU656 and YCrCb 4:2:2 [http://en.w...

2 14yrs

stephanusr

2 14yrs stephanusr

Xilinx ISE Multiple Drivers Error

Hi folks, I seem to have convinced ISE to output incorrect multiple-driver error messages. I've reduced the example to...

15 14yrs

chead

15 14yrs chead

banks and its association with options

oops, After discussing about the banks, it is certainly appropriate to take into account the monitoring of the options w...

0 14yrs

<Steve

0 14yrs <Steve

Spartan-6 66mhz pci

I'm trying to make a simple PCI interface in a XC6SLX45. In the end I'll probably go with the premade Xilinx core but I...

3 14yrs

jonpry

3 14yrs jonpry

Synthesis Problem

I have this code written in verilog for a counter but my program xilinx ise 14.1 finds 2 errors: ERROR:Xst:899 - "numar...

8 14yrs

andreiopariuc

8 14yrs andreiopariuc

FDE vs latch?

What's the big deal about a latch? Is it less efficient in floorspace than an FDE? Or is it just some amount of combinat...

6 14yrs

boat042-nospam

6 14yrs boat042-nospam

Re: Best way to get an array of vectors into a vector?

I agree Andy - making this into a function makes the code cleaner and is preferred if I would use this more than once.

1 14yrs

carwer0

1 14yrs carwer0

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