I'm learning the diff between variables and signals, and I've found this site:
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with a corresponding picture here:
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I've changed the source file to this
library ieee; use ieee.std_logic_1164.all;
entity sig_var is port ( d1, d2, d3 : in std_logic; res1, res2, res3 : out std_logic); end sig_var;
architecture behv of sig_var is signal sig_s1: std_logic; signal sig_s2: std_logic;
begin
proc1: process(d1,d2,d3) variable var_s1: std_logic;
begin var_s1 := d1 and d2; res1